# Can you design a chip? Announcing the protocol emulator ASIC competition

DevFeed: [Can you design a chip? Announcing the protocol emulator ASIC competition](<https://devfeed.tech/articles/can-you-design-a-chip-announcing-the-protocol-emulator-asic-competition-20207.md>)

Original publisher: [Read original article](<https://blog.janestreet.com/protocol-emulator-asic-competition/>)

Author: Benjamin Devlin

Published: 2026-09-10T00:00:00Z

Content type: release

Language: en

Sources: [Jane Street](<https://devfeed.tech/sources/jane-street.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Protocol (disambiguation)](<https://devfeed.tech/topics/protocol.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [Open Source](<https://devfeed.tech/topics/open-source.md>), [Emulator](<https://devfeed.tech/topics/emulator.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [Reverse Engineering](<https://devfeed.tech/topics/reverse-engineering.md>), [fpga](<https://devfeed.tech/topics/fpga.md>), [Formal methods](<https://devfeed.tech/topics/formal-methods.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>)

Tags: [chip-design](<https://devfeed.tech/tags/chip-design.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [emulator](<https://devfeed.tech/tags/emulator.md>), [ethernet](<https://devfeed.tech/tags/ethernet.md>), [firmware](<https://devfeed.tech/tags/firmware.md>), [formal-methods](<https://devfeed.tech/tags/formal-methods.md>), [fpga](<https://devfeed.tech/tags/fpga.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [i2c](<https://devfeed.tech/tags/i2c.md>), [jtag](<https://devfeed.tech/tags/jtag.md>), [open-source](<https://devfeed.tech/tags/open-source.md>), [peripheral](<https://devfeed.tech/tags/peripheral.md>), [protocol](<https://devfeed.tech/tags/protocol.md>), [reverse-engineering](<https://devfeed.tech/tags/reverse-engineering.md>)

## AI overview

Jane Street announces a competition to design an open-source, general-purpose protocol emulator ASIC. The proposed chip would use a small programmable CPU to read and write pins, count cycles, and implement protocols in firmware, with fabrication planned through IHP and Tiny Tapeout.

## Source excerpt

Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here's our next challenge! This time, you're designing the chip, and we'll pay to fabricate our favorite designs! We're particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies!