# ESP32 family Memory Map 101

DevFeed: [ESP32 family Memory Map 101](<https://devfeed.tech/articles/esp32-family-memory-map-101-13666.md>)

Original publisher: [Read original article](<https://developer.espressif.com/blog/2024/08/esp32-memory-map-101/>)

Author: John Lee

Published: 2024-08-20T00:00:00Z

Content type: tutorial

Language: en

Sources: [Blog on Developer Portal](<https://devfeed.tech/sources/blog-on-developer-portal.md>)

Topics: [ESP32](<https://devfeed.tech/topics/esp32.md>), [Espressif](<https://devfeed.tech/topics/espressif.md>), [Microcontroller](<https://devfeed.tech/topics/microcontroller.md>), [Zephyr RTOS](<https://devfeed.tech/topics/zephyr-rtos.md>), [Cache](<https://devfeed.tech/topics/cache.md>), [Development](<https://devfeed.tech/topics/development.md>)

Tags: [architecture](<https://devfeed.tech/tags/architecture.md>), [blog](<https://devfeed.tech/tags/blog.md>), [cache](<https://devfeed.tech/tags/cache.md>), [code](<https://devfeed.tech/tags/code.md>), [esp32](<https://devfeed.tech/tags/esp32.md>), [espressif](<https://devfeed.tech/tags/espressif.md>), [mcu](<https://devfeed.tech/tags/mcu.md>), [memory](<https://devfeed.tech/tags/memory.md>), [performance](<https://devfeed.tech/tags/performance.md>), [zephyr](<https://devfeed.tech/tags/zephyr.md>)

## AI overview

This article explains the ESP32 family's memory architecture and presents a visually structured compilation of information from datasheets and technical reference manuals. It covers memory maps, external flash and SPIRAM access, caches, ROM, SRAM, and related details relevant to low-level system and driver development, including Zephyr RTOS porting.

## Source excerpt

This article addresses the complexity of Espressif SoCs by offering a visual, structured compilation of crucial technical data from their datasheets and TRMs. The main takeaway for the reader is a simplified, actionable understanding of the memory maps, caches, peripherals, and eFuse blocks, which is essential for low-level system and driver development.