# Hardware Lock Elision on Haswell

DevFeed: [Hardware Lock Elision on Haswell](<https://devfeed.tech/articles/hardware-lock-elision-on-haswell-12450.md>)

Original publisher: [Read original article](<http://brooker.co.za/blog/2013/12/14/intel-hle.html>)

Author: Marc Brooker

Published: 2013-12-14T00:00:00Z

Content type: article

Language: en

Sources: [Marc Brooker's Blog](<https://devfeed.tech/sources/marc-brooker-s-blog.md>), [Marc Brooker's Blog](<https://devfeed.tech/sources/marc-brooker-s-blog-2.md>)

Topics: [Hardware](<https://devfeed.tech/topics/hardware.md>), [Concurrency](<https://devfeed.tech/topics/concurrency.md>), [intel](<https://devfeed.tech/topics/intel.md>), [Concurrent Programming](<https://devfeed.tech/topics/concurrent-programming.md>), [gcc](<https://devfeed.tech/topics/gcc.md>), [Assembly](<https://devfeed.tech/topics/assembly.md>)

Tags: [assembly](<https://devfeed.tech/tags/assembly.md>), [atomic](<https://devfeed.tech/tags/atomic.md>), [c](<https://devfeed.tech/tags/c.md>), [gcc](<https://devfeed.tech/tags/gcc.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [locks](<https://devfeed.tech/tags/locks.md>), [performance](<https://devfeed.tech/tags/performance.md>), [x86](<https://devfeed.tech/tags/x86.md>)

## AI overview

The article explores Intel Haswell's Hardware Lock Elision (HLE), a feature of TSX that can allow threads executing non-conflicting critical sections to proceed concurrently without serializing through a shared lock. It explains the XACQUIRE and XRELEASE instruction prefixes and shows how GCC 4.8 atomic builtins can emit them for a spinlock implementation.

## Source excerpt

Hardware Lock Elision on Haswell Exploring the performance of Intel's HLE A couple of months ago, I bought myself a new home PC, upgrading from my old Core2 Q6600 to a shiny new Haswell-based Xeon E3-1240v3. Honestly, I don't use my home PC that much, so the biggest draw for upgrading was trying out some of the features in Haswell, and getting loads of ECC RAM to support another project. The biggest thing I was excited about with Haswell is Intel's new TSX, a step towards true hardware transactional memory on commodity processors. Transactional memory is a very exciting idea, and seeing better support for it in hardware is really great. TSX provides two broad sets of functionality: restricted transactional memory (RTM), and hardware lock elision (HLE). HLE can be seen as a subset of RTM, offering backward compatibility with pre-Haswell processors. I started my investigations by looking at HLE. Intel describes Haswell's HLE like this: If multiple threads execute critical sections protected by the same lock but they do not perform any conflicting operations on eachother's data, then the threads can execute concurrently and without serialization. Even though the software uses lock acquisition operations on a common lock, the hardware is allowed to recognize this, elide the lock, and execute the critical sections on the two threads without requiring any communication through the lock if such communication was dynamically unnecessary. Based on this description, I was expecting HLE to work best on low-contention locks, possibly significantly increasing performance. Intel's backward-compatible HLE is based on two new instruction prefixes (rather than new instructions): XACQUIRE (F2) and XRELEASE (F3). You basically put the XACQUIRE prefix on the instruction that starts your critical section, and XRELEASE on the instruction that ends it. There are a bunch of good ways to implement locks on x86, but most commonly the start instruction will be an xcgh or cmpxchg, and the end