# Restricted Transactional Memory on Haswell

DevFeed: [Restricted Transactional Memory on Haswell](<https://devfeed.tech/articles/restricted-transactional-memory-on-haswell-12451.md>)

Original publisher: [Read original article](<http://brooker.co.za/blog/2013/12/16/intel-rtm.html>)

Author: Marc Brooker

Published: 2013-12-16T00:00:00Z

Content type: article

Language: en

Sources: [Marc Brooker's Blog](<https://devfeed.tech/sources/marc-brooker-s-blog.md>), [Marc Brooker's Blog](<https://devfeed.tech/sources/marc-brooker-s-blog-2.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [intel](<https://devfeed.tech/topics/intel.md>), [Concurrency](<https://devfeed.tech/topics/concurrency.md>), [Concurrent Programming](<https://devfeed.tech/topics/concurrent-programming.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [systems](<https://devfeed.tech/topics/systems.md>), [Clojure](<https://devfeed.tech/topics/clojure.md>)

Tags: [article](<https://devfeed.tech/tags/article.md>), [clojure](<https://devfeed.tech/tags/clojure.md>), [concurrency](<https://devfeed.tech/tags/concurrency.md>), [concurrent](<https://devfeed.tech/tags/concurrent.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [systems](<https://devfeed.tech/tags/systems.md>)

## AI overview

This article explores Intel's Restricted Transactional Memory (RTM), the other half of Intel TSX, on the Haswell processor. It explains how hardware can dynamically elide unnecessary lock synchronization, expose concurrency in lock-protected critical sections, and potentially improve performance in multicore systems. The article also contrasts RTM's compiler-builtin interface with software transactional memory and begins evaluating RTM using a chained hash-table test.

## Source excerpt

Restricted Transactional Memory on Haswell Exploring the performance of Intel's RTM In my last post, I looked at the performance of HLE on Intel's Haswell processor, and found that while it offered a nice speedup in some cases, it can cost performance in others. Still, Intel's TSX is an extremely exciting technology. In this post, I look at the other half of TSX, which Intel calls Restricted Transactional Memory. If you've never heard of transactional memory before, it's worth reading up. As usual, the Wikipedia article isn't a bad place to start. Some languages, like Clojure, offer software transactional memory out of the box. When it fits, STM can be an extremely nice way to write concurrent programs. The programming model can be simpler, and some classes of bugs (correctness, mostly, rather than liveness) are easier to avoid. Unlike all the great STM libraries, the current interfaces available to RTM, at least in the form of compiler builtins, don't offer much in the way of a simpler programming model. They do, however, offer us a great way to taste some of the performance benefits that Intel promises for RTM. First, let's take a look at what Intel says about RTM. Starting with the Intel® 64 and IA-32 Architectures Optimization Reference Manual: Intel® Transactional Synchronization Extensions (Intel TSX) aim to improve the performance of lock-protected critical sections while maintaining the lock-based programming model OK, so a simpler programming model isn't really Intel's aim here. I'm still pretty sure that there are great opportunities for TM libraries, some of which are already starting to appear, like xsync. Some more from the manual: Intel TSX allows the processor to determine dynamically whether threads need to serialize through lock-protected critical sections, and to perform serialization only when required. This lets hardware expose and exploit concurrency hidden in an application due to dynamically unnecessary synchronization through a technique know