# Synopsys Certifies A14 EDA Flows With TSMC and Tapes Out 64G UCIe on 2nm and 3nm, With PCIe 7.0 and HBM4 IP on N2P

DevFeed: [Synopsys Certifies A14 EDA Flows With TSMC and Tapes Out 64G UCIe on 2nm and 3nm, With PCIe 7.0 and HBM4 IP on N2P](<https://devfeed.tech/articles/synopsys-certifies-a14-eda-flows-with-tsmc-and-tapes-out-64g-ucie-on-2nm-and-3nm-with-pcie-7-0-and-hbm4-ip-on-n2p-61235.md>)

Original publisher: [Read original article](<https://www.storagereview.com/news/synopsys-tsmc-a14-certification-64g-ucie-tape-outs>)

Author: Harold Fritts

Published: 2026-09-28T15:40:05Z

Content type: news

Language: en

Sources: [StorageReview.com](<https://devfeed.tech/sources/storagereview-com.md>)

Topics: [tsmc](<https://devfeed.tech/topics/tsmc.md>), [CVE-2026-58058](<https://devfeed.tech/topics/cve-2026-58058.md>), [Agentic AI](<https://devfeed.tech/topics/what-is-agentic-ai.md>), [Shadcn UI](<https://devfeed.tech/topics/shadcn-ui.md>), [Open Source](<https://devfeed.tech/topics/open-source.md>)

Tags: [advanced-packaging](<https://devfeed.tech/tags/advanced-packaging.md>), [agentic](<https://devfeed.tech/tags/agentic.md>), [agentic-ai](<https://devfeed.tech/tags/agentic-ai.md>), [ai](<https://devfeed.tech/tags/ai.md>), [ai-design](<https://devfeed.tech/tags/ai-design.md>), [ai-systems](<https://devfeed.tech/tags/ai-systems.md>), [co-packaged-optics](<https://devfeed.tech/tags/co-packaged-optics.md>), [ecosystem](<https://devfeed.tech/tags/ecosystem.md>), [eda](<https://devfeed.tech/tags/eda.md>), [enterprise](<https://devfeed.tech/tags/enterprise.md>), [high-performance](<https://devfeed.tech/tags/high-performance.md>), [high-performance-computing](<https://devfeed.tech/tags/high-performance-computing.md>), [implementation](<https://devfeed.tech/tags/implementation.md>), [integrated-voltage-regulator](<https://devfeed.tech/tags/integrated-voltage-regulator.md>), [interconnect](<https://devfeed.tech/tags/interconnect.md>), [optics](<https://devfeed.tech/tags/optics.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [set](<https://devfeed.tech/tags/set.md>), [synopsys](<https://devfeed.tech/tags/synopsys.md>), [tsmc](<https://devfeed.tech/tags/tsmc.md>)

## AI overview

Synopsys certified digital and analog EDA flows for TSMC's A14 process and completed 64G UCIe IP tape-outs on TSMC's 2nm and 3nm nodes. Their broader collaboration also includes agentic AI-assisted design tools, CoWoS power-delivery co-design, and photonic and electronic co-design for co-packaged optics.

## Source excerpt

Synopsys has certified its digital and analog EDA flows on TSMC's A14 process and completed 64G UCIe IP tape-outs on TSMC's 2nm and 3nm nodes, the two hard milestones in a broader set of joint work the companies announced around TSMC's Open Innovation Platform ecosystem. The rest of the payload covers agentic AI design flows The post Synopsys Certifies A14 EDA Flows With TSMC and Tapes Out 64G UCIe on 2nm and 3nm, With PCIe 7.0 and HBM4 IP on N2P appeared first on StorageReview.com.