# Chips and Cheese The Devil is in the Details! Deep dives into computer hardware and software and the wider industry... This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## On Binary Translation and its Consequences DevFeed: [On Binary Translation and its Consequences]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-09-10T09:46:18Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [cpu](), [x86](), [Arm](), [Benchmark](), [Windows](), [Emulator](), [pc](), [Microsoft](), [Azure]() Tags: [arm](), [benchmark](), [cpu](), [emulator](), [hardware](), [microsoft](), [microsoft-azure](), [pc](), [windows](), [x86]() ### AI overview This article examines the performance cost of running x86-64 software through Windows 11's Prism binary translator on Arm-based PCs. Using Geekbench 7, it compares translated x86-64 workloads with native Arm performance while noting that the benchmark represents only a limited range of applications. ### Source excerpt The PC market is one of the toughest areas for a CPU designer to compete in. ## Arm's C2-Ultra, G2-Ultra NX, and CSS N4 IP DevFeed: [Arm's C2-Ultra, G2-Ultra NX, and CSS N4 IP]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-09-08T02:00:00Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Arm](), [cpu](), [Hardware](), [Support]() Tags: [arm](), [cpu](), [hardware](), [performance]() ### AI overview The article examines Arm's C2-Ultra CPU core, G2-Ultra NX GPU IP, and Neoverse CSS N4 IP. It compares C2-Ultra with earlier Arm cores and discusses claimed performance gains, while noting that the figures come from FPGA simulations and depend partly on clock speed and cache configuration. An editor's note states that the maximum IPC increase over C1-Ultra is 7% under the cited parameters. ### Source excerpt Editor's Note (9/8/2026): Arm has reached out to clarify that the maximum IPC increase of the C2-Ultra core over the C1-Ultra core using the parameters shown in the endnotes is 7% along with the memory bandwidth improvement not factoring into the IPC improvement. ## Hot Chips 2026: Interviewing IBM's Christian Zoellin & Christian Jacobi DevFeed: [Hot Chips 2026: Interviewing IBM's Christian Zoellin & Christian Jacobi]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-30T17:31:05Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Arm](), [ibm](), [systems]() Tags: [2026](), [architecture](), [architectures](), [arm](), [core](), [decoding](), [ibm](), [interviewing](), [systems]() ### AI overview An interview with IBM engineers at Hot Chips 2026 discusses the company's next-generation z/Architecture processor, which supports both the z/Architecture and Arm instruction sets. The conversation covers its shared decode pipeline, separate instruction decoders, and handling of differing endianness in the load-store unit. ### Source excerpt Hello you fine Internet folks, ## Hot Chips 2026: XCENA and Samsung's Near-Memory Compute CXL Device DevFeed: [Hot Chips 2026: XCENA and Samsung's Near-Memory Compute CXL Device]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-30T07:25:37Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [samsung](), [ddr5](), [RISC-V](), [data](), [Cache](), [Arm](), [intel]() Tags: [2026](), [arm](), [cache](), [capacity](), [clusters](), [compute](), [core](), [ddr5](), [dram](), [intel](), [memory](), [parallel](), [pcie](), [performance](), [risc-v](), [samsung]() ### AI overview The article examines XCENA and Samsung's MX1, a CXL memory expansion device that can host up to 2 TB of DDR5 memory, connect SSDs, and provide onboard compute through 3,072 RISC-V cores. It describes the device's memory bandwidth, cache hierarchy, power use, and focus on data-parallel workloads. ### Source excerpt CXL memory expansion, with a side of compute ## Hot Chips 2026: Samsung's Processing-in-Memory (PIM) DevFeed: [Hot Chips 2026: Samsung's Processing-in-Memory (PIM)]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-29T05:36:33Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [samsung](), [Latency]() Tags: [2026](), [compute](), [dram](), [latency](), [memory](), [model](), [operations](), [parallel](), [precision](), [samsung]() ### AI overview The article examines Samsung's LPDDR5X Processing-in-Memory implementation presented at Hot Chips 2026. It describes PIM blocks placed in each DRAM bank, enabling access to internal memory bandwidth and supporting MAC computations near the data. ### Source excerpt In-memory compute with LPDDR5X ## Hot Chips 2026: Intel's Crescent Island DevFeed: [Hot Chips 2026: Intel's Crescent Island]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-27T05:12:31Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [intel](), [GPU](), [Artificial Intelligence](), [datacenter](), [Blackwell](), [deepseek]() Tags: [2026](), [ai](), [amd](), [blackwell](), [datacenter](), [deepseek](), [gpu](), [intel]() ### AI overview The article discusses Intel's upcoming Crescent Island datacenter GPU, focusing on its LPDDR5X-based memory subsystem, reported capacity of up to 480 GB, undisclosed memory bandwidth, Xe3P architecture, and full-rate FP64 support. It also compares aspects of the design with competing GPUs. ### Source excerpt Hello you fine Internet folks, ## Hot Chips 2026: Fujitsu's Monaka CPU DevFeed: [Hot Chips 2026: Fujitsu's Monaka CPU]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-26T01:20:30Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [cpu](), [Arm](), [Algorithm](), [intel]() Tags: [2026](), [algorithm](), [amd](), [arm](), [cpu](), [fujitsu](), [hpc](), [intel](), [processor]() ### AI overview The article examines Fujitsu's Monaka CPU, which is intended to improve on A64FX's limitations for general-purpose workloads while retaining strong HPC vector throughput. It discusses Monaka's three-level TAGE branch predictor and contrasts it with A64FX's perceptron-like predictor. ### Source excerpt Building on a long history of HPC-focused cores, and looking beyond HPC ## Hot Chips 2026: Intel's Diamond Rapids DevFeed: [Hot Chips 2026: Intel's Diamond Rapids]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-25T06:20:03Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [cpu](), [intel](), [Cache](), [IO](), [x86]() Tags: [2026](), [cache](), [cpu](), [intel](), [io](), [processor](), [x86]() ### AI overview The article examines Intel's Diamond Rapids server CPU, including its 3D-stacked L3 cache, die and packaging design, revised 256-core specification, 1.6 TB/s memory bandwidth, 128 PCIe Gen 6 lanes, and two new x86 ISA extensions. It compares these characteristics with AMD's Venice processor. ### Source excerpt Hello you fine Internet folks, ## SiFive's First Server Platform DevFeed: [SiFive's First Server Platform]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-25T01:48:39Z Content type: comparison Language: en Sources: [Chips and Cheese]() Topics: [RISC-V](), [servers](), [cpu](), [ddr5](), [Ubuntu](), [intel]() Tags: [cpu](), [ddr5](), [intel](), [performance](), [risc-v](), [server](), [ubuntu]() ### AI overview The article examines SiFive's BigSky SF-2U870, a 2U RISC-V server platform with 32 P870-D cores, DDR5 memory, PCIe connectivity, GPU support, and storage. It describes the platform as easy to deploy, highlights RVA23 and Ubuntu 26.04 support, and compares its specifications with Intel's Xeon 6532P-B and AMD EPYC 8325P. ### Source excerpt Hello you fine Internet folks, ## Hot Chips 2026: Intel's Wildcat Lake DevFeed: [Hot Chips 2026: Intel's Wildcat Lake]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-24T19:50:30Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [intel](), [cpu](), [GPU](), [SOC](), [Bluetooth]() Tags: [2026](), [architecture](), [battery](), [bluetooth](), [core](), [cost](), [cpu](), [gpu](), [intel](), [platform](), [processors](), [soc](), [technologies](), [technology](), [wifi](), [wildcat-lake]() ### AI overview This article examines how Intel designed Wildcat Lake, also called Core Series 3, as a lower-cost mobile processor platform. It describes the use of new CPU cores, Xe3 graphics, IO, a multi-chip package, a distinct platform, and selected feature trade-offs to reduce costs while retaining capabilities important to battery life and connectivity. ### Source excerpt All about making things affordable ## Hot Chips 2026: CUDA Targets RISC-V DevFeed: [Hot Chips 2026: CUDA Targets RISC-V]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-24T16:49:25Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [CUDA](), [RISC-V](), [Nvidia](), [GPU](), [Software]() Tags: [cache](), [cuda](), [framework](), [gpu](), [nvidia](), [pcie](), [risc-v](), [software](), [uefi]() ### AI overview The article reports that Nvidia is exploring support for CUDA on RISC-V CPUs. It describes requirements including RVA23, server SoC and platform specifications, RISC-V ACPI support, vector extensions, and PCIe coherency to support reliable and efficient GPU compute. ### Source excerpt CUDA is the most important software framework in the GPU compute world, and Nvidia is looking at supporting CUDA on RISC-V. Terms and conditions may apply. ## Hot Chips 2026: Applying High Bandwidth Flash (HBF) DevFeed: [Hot Chips 2026: Applying High Bandwidth Flash (HBF)]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-23T22:51:05Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Machine Learning & Artificial Intelligence](), [Inference](), [vllm](), [moe](), [Cache]() Tags: [2026](), [dram](), [machine-learning](), [memory](), [moe](), [ssd](), [vllm]() ### AI overview This article examines how High Bandwidth Flash (HBF) could support machine learning workloads. HBF does not yet have products; the discussion uses simulations and projections to explore software strategies, including moving Mixture-of-Experts components or KV cache data between HBF and faster memory, with vLLM as an example. ### Source excerpt Machine learning workloads have an insatiable appetite for DRAM capacity. Flash memory is cheaper per gigabyte of capacity than DRAM. Could it offer a way out? ## Hot Chips 2026: Samsung and HBM Base Die Opportunities DevFeed: [Hot Chips 2026: Samsung and HBM Base Die Opportunities]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-23T19:01:23Z Content type: news Language: en Sources: [Chips and Cheese]() Topics: [samsung]() Tags: [capacity](), [cpu](), [intel](), [machine-learning](), [memory](), [samsung]() ### AI overview The article discusses Samsung's HBM base-die design. Samsung moved HBM4 and HBM4E base dies to a 4nm logic process, creating additional usable area and enabling potential optimizations such as moving the memory controller onto the HBM base die. ### Source excerpt Machine learning applications demand ever more memory capacity and bandwidth. Samsung responded by fabricating their HBM base dies on a logic node, which opens up more opportunities ## Talking with Synopsys about the Physics of Chip Design at DAC 2026 DevFeed: [Talking with Synopsys about the Physics of Chip Design at DAC 2026]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-11T16:52:16Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Chip design](), [3D](), [Simulation and Design]() Tags: [3d](), [audio](), [automotive](), [battery](), [chip-design](), [communications](), [design](), [desktop](), [heat](), [interview](), [low-power](), [physics](), [techniques]() ### AI overview An edited audio interview with Synopsys executive Ravi Subramanian examines the physics involved in chip design and electronic design automation tools. The discussion covers larger chips, 2.5D and 3D multi-die integration, thermal management, low-power mobile systems, and automotive operating environments. ### Source excerpt Hello you fine Internet folks, ## NVIDIA's Vera Whitepaper Describes an Ambitious Arm Server CPU but Overstates Its Performance Case DevFeed: [NVIDIA's Vera Whitepaper Describes an Ambitious Arm Server CPU but Overstates Its Performance Case]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-05T19:19:22Z Content type: opinion Language: en Sources: [Chips and Cheese]() Topics: [Nvidia](), [cpu](), [Arm](), [Hardware](), [Cache](), [x86]() Tags: [amd](), [arm](), [cache](), [cpu](), [hardware](), [nvidia](), [x86]() ### AI overview The article examines NVIDIA's Vera whitepaper, focusing on the 88-core Arm-based server CPU and its Olympus core design. It argues that Vera's hardware appears impressive, while criticizing the whitepaper for using questionable comparisons and unsupported interpretations of performance data. ### Source excerpt Hello you fine Internet folks, ## Arm's Cortex A55 DevFeed: [Arm's Cortex A55]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-02T22:02:44Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Arm](), [Front end](), [Cache](), [Neural Network]() Tags: [arm](), [cache](), [core](), [cortex-a55](), [devices](), [efficiency](), [floating-point](), [frontend](), [linux](), [memory](), [neural](), [performance]() ### AI overview A technical analysis of Arm's Cortex A55 examines its microarchitecture, including its in-order pipelines, frontend, memory subsystem, branch prediction, and implementations in the MediaTek Genio 1200 and other devices. ### Source excerpt Arm's 5-series cores are meant for tasks where performance barely matters, but power and area efficiency are top priorities. ## Intel Reportedly Provides RosaicLabs with Atom RTL as Linux Posts Describe 32-Tile AMX x86 Implementations DevFeed: [Intel Reportedly Provides RosaicLabs with Atom RTL as Linux Posts Describe 32-Tile AMX x86 Implementations]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-07-31T01:39:23Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Atom](), [x86](), [intel](), [cpu]() Tags: [cpu](), [intel](), [processor](), [x86]() ### AI overview The article examines reports that Intel is providing RosaicLabs with register-transfer-level code for Atom CPU technology, alongside Linux kernel posts describing x86 implementations with 16 and 32 AMX tile registers. It distinguishes reported facts from speculation linking the startup to the implementation. ### Source excerpt Hello you fine Internet folks, ## AMD Advancing AI 2026: Talking CDNA5 with AMD's Alan Smith DevFeed: [AMD Advancing AI 2026: Talking CDNA5 with AMD's Alan Smith]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-07-27T19:43:53Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Artificial Intelligence](), [GPU](), [datacenter](), [Optimization](), [Cache]() Tags: [ai](), [cache](), [data-center](), [gpu](), [optimization]() ### AI overview An interview with AMD Corporate Fellow and Chief Architect Alan Smith about the CDNA5 architecture. Smith discusses moving the architecture from GCN toward RDNA, improving the cache and execution systems, increasing efficiency, and bringing AMD's gaming and data-center GPU roadmaps closer together for future optimization. ### Source excerpt Hello you fine Internet folks, ## AMD Instinct MI455X GPU Detailed for Rack-Scale AI Deployments DevFeed: [AMD Instinct MI455X GPU Detailed for Rack-Scale AI Deployments]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-07-23T17:37:10Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [GPU](), [Artificial Intelligence](), [networking](), [NVLink](), [systems](), [Ethernet](), [SOC](), [tsmc]() Tags: [2026](), [ai](), [architecture](), [article](), [capacity](), [communication](), [compute](), [ethernet](), [gpu](), [memory](), [networking](), [performance](), [processors](), [scale](), [soc](), [tsmc]() ### AI overview The article examines AMD's Instinct MI455X, a CDNA5 GPU designed for rack-scale AI deployments. It describes the Helios rack-scale system, UALink over Ethernet networking, compute and memory specifications, and changes to the WGP, register-file, and matrix-unit designs. ### Source excerpt Editor's Note (7/25/2026): The article has been edited with more information about the L2 behavior along with the bandwidth of the die to die interface. ## LLVM Analysis of the Differences Between AMD GFX1250 and GFX1251 DevFeed: [LLVM Analysis of the Differences Between AMD GFX1250 and GFX1251]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-07-20T09:23:59Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [LLVM](), [Compiler](), [Hardware]() Tags: [compiler](), [hardware](), [llvm](), [math](), [memory](), [vector]() ### AI overview The article examines LLVM target descriptions for AMD GFX1250 and GFX1251, identifying their shared GFX12.5 features and differences. It focuses on GFX1251's improved 64-bit execution, packed FP64 and U64 instructions, and the compiler cost model's support for those operations. ### Source excerpt Hello you fine Internet folks, this article is a sequel to the Scrying the AMD GFX1250 LLVM Tea Leaves article where we are going to look at the differences between GFX1250 and GFX1251.