# Performance Matters

A blog about low-level software and hardware performance.

This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles.

## Intel microcode update disabled a hardware zero-store optimization on Skylake and Ice Lake

DevFeed: [Intel microcode update disabled a hardware zero-store optimization on Skylake and Ice Lake](<https://devfeed.tech/articles/your-cpu-may-have-slowed-down-on-wednesday-28491.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2021/06/17/rip-zero-opt.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2021-06-17T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [intel](<https://devfeed.tech/topics/intel.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [benchmarking](<https://devfeed.tech/topics/benchmarking.md>), [Linux](<https://devfeed.tech/topics/linux.md>), [Security](<https://devfeed.tech/topics/security.md>), [Ubuntu](<https://devfeed.tech/topics/ubuntu.md>)

Tags: [benchmark](<https://devfeed.tech/tags/benchmark.md>), [blog](<https://devfeed.tech/tags/blog.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [intel](<https://devfeed.tech/tags/intel.md>), [linux](<https://devfeed.tech/tags/linux.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [security](<https://devfeed.tech/tags/security.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [ubuntu](<https://devfeed.tech/tags/ubuntu.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

An Intel microcode update delivered through Ubuntu 20.04 disabled a hardware zero-store optimization on Skylake and Ice Lake processors, apparently to mitigate CVE-2020-24512. Benchmarks showed slower zero-filling after the update, highlighting that microcode changes can affect CPU performance and benchmark reproducibility.

### Source excerpt

The death of hardware store optimization.

## Ice Lake AVX-512 Downclocking

DevFeed: [Ice Lake AVX-512 Downclocking](<https://devfeed.tech/articles/ice-lake-avx-512-downclocking-28490.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-08-19T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [intel](<https://devfeed.tech/topics/intel.md>), [floating-point](<https://devfeed.tech/topics/floating-point.md>), [Rocket](<https://devfeed.tech/topics/rocket.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [avx512](<https://devfeed.tech/tags/avx512.md>), [blog](<https://devfeed.tech/tags/blog.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [floating-point](<https://devfeed.tech/tags/floating-point.md>), [icelake](<https://devfeed.tech/tags/icelake.md>), [intel](<https://devfeed.tech/tags/intel.md>), [performance](<https://devfeed.tech/tags/performance.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This technical post investigates AVX2- and AVX-512-related license-based downclocking on Intel Ice Lake and Rocket Lake CPUs. Measurements from an Ice Lake i5-1035G4 indicate little frequency reduction from wider instructions, with a reported 100 MHz decrease in one single-core case.

### Source excerpt

Examining the extent of AVX related downclocking on Intel's Ice Lake CPU

## A Concurrency Cost Hierarchy

DevFeed: [A Concurrency Cost Hierarchy](<https://devfeed.tech/articles/a-concurrency-cost-hierarchy-28489.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/07/06/concurrency-costs.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-07-06T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [Concurrency](<https://devfeed.tech/topics/concurrency.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>)

Tags: [benchmark](<https://devfeed.tech/tags/benchmark.md>), [blog](<https://devfeed.tech/tags/blog.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [concurrency](<https://devfeed.tech/tags/concurrency.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [threads](<https://devfeed.tech/tags/threads.md>)

### AI overview

This article presents a six-level hierarchy for reasoning about the performance costs of concurrent operations, from fast to slow. It uses safely incrementing a shared counter across threads as a practical example and provides benchmark source, results, and hardware context.

### Source excerpt

Concurrent operations can be grouped relatively neatly into categories based on their cost

## AVX-512 Mask Registers, Again

DevFeed: [AVX-512 Mask Registers, Again](<https://devfeed.tech/articles/avx-512-mask-registers-again-28488.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/05/26/kreg2.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-05-26T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [intel](<https://devfeed.tech/topics/intel.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [avx512](<https://devfeed.tech/tags/avx512.md>), [blog](<https://devfeed.tech/tags/blog.md>), [compare](<https://devfeed.tech/tags/compare.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [vector](<https://devfeed.tech/tags/vector.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

The article revisits AVX-512 mask registers by examining an SKX processor die shot. It uses visual comparisons of register-file layouts and related processor dies to investigate whether a highlighted mystery block is the physical mask-register file.

### Source excerpt

Taking a second look at the newly introduced mask registers, this time with the benefit of a SKX die shot from Fritzchens Fritz.

## Ice Lake Store Elimination

DevFeed: [Ice Lake Store Elimination](<https://devfeed.tech/articles/ice-lake-store-elimination-28487.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/05/18/icelake-zero-opt.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-05-18T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [intel](<https://devfeed.tech/topics/intel.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [x86](<https://devfeed.tech/topics/x86.md>), [Compiler](<https://devfeed.tech/topics/compiler.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>)

Tags: [analysis](<https://devfeed.tech/tags/analysis.md>), [avx](<https://devfeed.tech/tags/avx.md>), [blog](<https://devfeed.tech/tags/blog.md>), [compiler](<https://devfeed.tech/tags/compiler.md>), [icelake](<https://devfeed.tech/tags/icelake.md>), [intel](<https://devfeed.tech/tags/intel.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This article analyzes zero-store optimization on Intel's Ice Lake architecture. It compares performance results across memory regions and examines how compiler-generated 512-bit versus 256-bit instructions, including AVX-512 clocking effects, influence the observed behavior.

### Source excerpt

We look at the zero store optimization as it applies to Intel's newest micro-architecture.

## Hardware Store Elimination

DevFeed: [Hardware Store Elimination](<https://devfeed.tech/articles/hardware-store-elimination-28486.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/05/13/intel-zero-opt.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-05-13T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [Hardware](<https://devfeed.tech/topics/hardware.md>), [intel](<https://devfeed.tech/topics/intel.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [x86](<https://devfeed.tech/topics/x86.md>)

Tags: [benchmark](<https://devfeed.tech/tags/benchmark.md>), [blog](<https://devfeed.tech/tags/blog.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This article investigates a previously undocumented zero-related optimization on Intel CPUs. It begins with memory benchmarks and examines whether the values written to memory can affect performance, despite the usual assumption that only memory addresses and caching behavior matter.

### Source excerpt

Probing a previously undocumented zero-related optimization on Intel CPUs.

## Adding Staticman Comments

DevFeed: [Adding Staticman Comments](<https://devfeed.tech/articles/adding-staticman-comments-28485.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/02/05/now-with-comments.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-02-05T00:00:00Z

Content type: tutorial

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [GitHub](<https://devfeed.tech/topics/github.md>), [GitHub Pages](<https://devfeed.tech/topics/github-pages.md>), [Bot](<https://devfeed.tech/topics/bot.md>), [Pull Request](<https://devfeed.tech/topics/pull-request.md>), [Heroku](<https://devfeed.tech/topics/heroku.md>), [personal access token](<https://devfeed.tech/topics/personal-access-token.md>), [hosting](<https://devfeed.tech/topics/hosting.md>), [repo](<https://devfeed.tech/topics/repo.md>)

Tags: [blog](<https://devfeed.tech/tags/blog.md>), [file](<https://devfeed.tech/tags/file.md>), [github](<https://devfeed.tech/tags/github.md>), [github-pages](<https://devfeed.tech/tags/github-pages.md>), [guide](<https://devfeed.tech/tags/guide.md>), [heroku](<https://devfeed.tech/tags/heroku.md>), [hosting](<https://devfeed.tech/tags/hosting.md>), [meta](<https://devfeed.tech/tags/meta.md>), [personal-access-token](<https://devfeed.tech/tags/personal-access-token.md>), [pull-request](<https://devfeed.tech/tags/pull-request.md>), [static-site](<https://devfeed.tech/tags/static-site.md>), [staticman](<https://devfeed.tech/tags/staticman.md>)

### AI overview

A tutorial explaining how to add Staticman comments to a static blog. It covers the submission flow, deploying the API bridge on Heroku, using GitHub pull requests to store comments, and republishing through GitHub Pages.

### Source excerpt

Adding static comments to a static blog using staticman. Static.

## How C++ Standard Library Implementations Optimize Zero-Filling

DevFeed: [How C++ Standard Library Implementations Optimize Zero-Filling](<https://devfeed.tech/articles/the-hunt-for-the-fastest-zero-28484.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/01/20/zero.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-01-20T00:00:00Z

Content type: opinion

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [C++](<https://devfeed.tech/topics/c-plus-plus.md>), [Library](<https://devfeed.tech/topics/library.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [implementation](<https://devfeed.tech/topics/implementation.md>), [gcc](<https://devfeed.tech/topics/gcc.md>)

Tags: [blog](<https://devfeed.tech/tags/blog.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [compiler-optimization](<https://devfeed.tech/tags/compiler-optimization.md>), [gcc](<https://devfeed.tech/tags/gcc.md>), [implementation](<https://devfeed.tech/tags/implementation.md>), [library](<https://devfeed.tech/tags/library.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>)

### AI overview

This article examines why different C++ ways of filling an array with zeros can have substantially different performance. It explains that a standard-library implementation may recognize a special case and use a more efficient bulk operation, with the observed result depending on the compiler, optimization level, and hardware.

### Source excerpt

Unexpected performance deviations depending on how you spell zero.

## Investigating AVX-512 Frequency Transitions on Intel CPUs

DevFeed: [Investigating AVX-512 Frequency Transitions on Intel CPUs](<https://devfeed.tech/articles/gathering-intel-on-intel-avx-512-transitions-28483.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-01-17T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [intel](<https://devfeed.tech/topics/intel.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [Linux](<https://devfeed.tech/topics/linux.md>), [Code](<https://devfeed.tech/topics/code.md>), [Script](<https://devfeed.tech/topics/script.md>), [Scripting](<https://devfeed.tech/topics/scripting.md>), [Shell](<https://devfeed.tech/topics/shell.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [benchmark](<https://devfeed.tech/tags/benchmark.md>), [blog](<https://devfeed.tech/tags/blog.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [code](<https://devfeed.tech/tags/code.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [linux](<https://devfeed.tech/tags/linux.md>), [metrics](<https://devfeed.tech/tags/metrics.md>), [performance](<https://devfeed.tech/tags/performance.md>), [python](<https://devfeed.tech/tags/python.md>), [scripting](<https://devfeed.tech/tags/scripting.md>), [shell](<https://devfeed.tech/tags/shell.md>), [tests](<https://devfeed.tech/tags/tests.md>), [uarch](<https://devfeed.tech/tags/uarch.md>)

### AI overview

This article investigates the detailed behavior of AVX and AVX-512 frequency transitions on Intel CPUs using target tests and sampled performance metrics. It describes the test structure and provides accompanying source code and data-generation scripts.

### Source excerpt

Investigating some details of SIMD related frequency transitions on Intel CPUs.

## A Note on Mask Registers

DevFeed: [A Note on Mask Registers](<https://devfeed.tech/articles/a-note-on-mask-registers-28482.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2019/12/05/kreg-facts.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2019-12-05T16:30:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [Hardware](<https://devfeed.tech/topics/hardware.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [intel](<https://devfeed.tech/topics/intel.md>), [Cache](<https://devfeed.tech/topics/cache.md>)

Tags: [architecture](<https://devfeed.tech/tags/architecture.md>), [avx](<https://devfeed.tech/tags/avx.md>), [blog](<https://devfeed.tech/tags/blog.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [cache](<https://devfeed.tech/tags/cache.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [execution](<https://devfeed.tech/tags/execution.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [performance](<https://devfeed.tech/tags/performance.md>), [uarch](<https://devfeed.tech/tags/uarch.md>)

### AI overview

This article examines AVX-512 mask registers and investigates the size of their physical register file using an updated out-of-order CPU resource probing tool. It explains zero-masking and merging behavior and introduces a method based on measuring whether cache-miss loads execute in parallel.

### Source excerpt

Some mostly too-low-level-to-care-about hardware details of the mask registers introduced in AVX-512.