# A7

Published articles for A7.

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## How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å

DevFeed: [How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å](<https://devfeed.tech/articles/how-self-aligned-cfet-technology-could-extend-cmos-scaling-beyond-10-a-95101.md>)

Original publisher: [Read original article](<https://semiengineering.com/how-self-aligned-cfet-technology-could-extend-cmos-scaling-beyond-10-a/>)

Author: Qingpeng Wang

Published: 2026-10-22T07:05:02Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>)

Tags: [3d](<https://devfeed.tech/tags/3d.md>), [a7](<https://devfeed.tech/tags/a7.md>), [architecture](<https://devfeed.tech/tags/architecture.md>), [architectures](<https://devfeed.tech/tags/architectures.md>), [area](<https://devfeed.tech/tags/area.md>), [blogs-md](<https://devfeed.tech/tags/blogs-md.md>), [cfet](<https://devfeed.tech/tags/cfet.md>), [channel](<https://devfeed.tech/tags/channel.md>), [channel-width](<https://devfeed.tech/tags/channel-width.md>), [cmos](<https://devfeed.tech/tags/cmos.md>), [complementary-fet](<https://devfeed.tech/tags/complementary-fet.md>), [effective](<https://devfeed.tech/tags/effective.md>), [electrostatics](<https://devfeed.tech/tags/electrostatics.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [lam-research](<https://devfeed.tech/tags/lam-research.md>), [logic](<https://devfeed.tech/tags/logic.md>), [manufacturing-packaging-and-materials](<https://devfeed.tech/tags/manufacturing-packaging-and-materials.md>), [perfecting-the-process](<https://devfeed.tech/tags/perfecting-the-process.md>), [performance](<https://devfeed.tech/tags/performance.md>), [process](<https://devfeed.tech/tags/process.md>), [scaling](<https://devfeed.tech/tags/scaling.md>), [self-aligned](<https://devfeed.tech/tags/self-aligned.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [sequence](<https://devfeed.tech/tags/sequence.md>), [sram](<https://devfeed.tech/tags/sram.md>), [technology](<https://devfeed.tech/tags/technology.md>)

### AI overview

The proposed self-aligned CFET (SA-CFET) stacks NMOS and PMOS devices vertically and uses self-aligned buried power rail, contact, and through-silicon-via modules to address contact crowding and overlay sensitivity. SEMulator3D digital-twin process modeling demonstrated 6T SRAM and logic cells, including NOT, NAND, and NOR, with a modeled SRAM bit cell area of 0.0094 μm²--52.7% smaller than N3 and 19% smaller than cited A7 CFET designs. The excerpt also reports at least a 10 nm overlay window across critical contact layers without modeled open or short failures. The authors say the design maintains N3 specifications and may support scaling at 10 Å and beyond; these are simulation results and a proposed scaling path, not reported fabrication results.

### Source excerpt

A process sequence for SRAM and logic that delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes. The post How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å appeared first on Semiconductor Engineering.

## Comparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials)

DevFeed: [Comparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials)](<https://devfeed.tech/articles/comparing-a7-cfet-and-a10-nanosheet-fets-from-parasitics-to-chip-reliability-tum-unimore-applied-materials-60256.md>)

Original publisher: [Read original article](<https://semiengineering.com/comparing-a7-cfet-and-a10-nanosheet-fets-from-parasitics-to-chip-reliability-tum-unimore-applied-materials/>)

Author: Technical Paper Link

Published: 2026-09-25T22:29:43Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Simulation and Design](<https://devfeed.tech/topics/simulation-and-design.md>), [implementation](<https://devfeed.tech/topics/implementation.md>), [3D](<https://devfeed.tech/topics/3d.md>), [Artificial Intelligence](<https://devfeed.tech/topics/ai.md>)

Tags: [2026](<https://devfeed.tech/tags/2026.md>), [a10](<https://devfeed.tech/tags/a10.md>), [a7](<https://devfeed.tech/tags/a7.md>), [advanced-process-nodes](<https://devfeed.tech/tags/advanced-process-nodes.md>), [aging](<https://devfeed.tech/tags/aging.md>), [ai-accelerator](<https://devfeed.tech/tags/ai-accelerator.md>), [ai-accelerators](<https://devfeed.tech/tags/ai-accelerators.md>), [applied-materials](<https://devfeed.tech/tags/applied-materials.md>), [bias-temperature-instability](<https://devfeed.tech/tags/bias-temperature-instability.md>), [bti](<https://devfeed.tech/tags/bti.md>), [cfet](<https://devfeed.tech/tags/cfet.md>), [chip](<https://devfeed.tech/tags/chip.md>), [complementary-fet](<https://devfeed.tech/tags/complementary-fet.md>), [design-verification](<https://devfeed.tech/tags/design-verification.md>), [engineering](<https://devfeed.tech/tags/engineering.md>), [gaa](<https://devfeed.tech/tags/gaa.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [materials](<https://devfeed.tech/tags/materials.md>), [multiphysics](<https://devfeed.tech/tags/multiphysics.md>), [nanosheet-fet](<https://devfeed.tech/tags/nanosheet-fet.md>), [nsfet](<https://devfeed.tech/tags/nsfet.md>), [paper](<https://devfeed.tech/tags/paper.md>), [parasitic-capacitance](<https://devfeed.tech/tags/parasitic-capacitance.md>), [parasitic-resistance](<https://devfeed.tech/tags/parasitic-resistance.md>), [physics](<https://devfeed.tech/tags/physics.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [reliability](<https://devfeed.tech/tags/reliability.md>), [rtl](<https://devfeed.tech/tags/rtl.md>), [rtl-to-gds](<https://devfeed.tech/tags/rtl-to-gds.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [standard-cell](<https://devfeed.tech/tags/standard-cell.md>), [standard-cells](<https://devfeed.tech/tags/standard-cells.md>), [stco](<https://devfeed.tech/tags/stco.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [technical-university-of-munich](<https://devfeed.tech/tags/technical-university-of-munich.md>), [thermal-analysis](<https://devfeed.tech/tags/thermal-analysis.md>), [transistor-scaling](<https://devfeed.tech/tags/transistor-scaling.md>), [transistors](<https://devfeed.tech/tags/transistors.md>), [university-of-modena-and-reggio-emilia](<https://devfeed.tech/tags/university-of-modena-and-reggio-emilia.md>)

### AI overview

A technical paper compares A7 CFET and A10 NSFET technologies using a physics-based system-technology co-evaluation flow. The analysis covers parasitic RC extraction, standard-cell generation, RTL-to-GDS implementation for an AI accelerator, thermal behavior, and BTI aging.

### Source excerpt

Researchers at the TU Munich, University of Modena and Reggio Emilia, and Applied Materials published a technical paper titled "System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability." Abstract Excerpt: " In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in... " read more The post Comparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials) appeared first on Semiconductor Engineering.