# Accelerators Published articles for Accelerators. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## d-Matrix Joins the NVIDIA NVLink Fusion Platform DevFeed: [d-Matrix Joins the NVIDIA NVLink Fusion Platform]() Original publisher: [Read original article]() Author: Cliff Robinson Published: 2026-09-12T21:42:59Z Content type: news Language: en Sources: [ServeTheHome]() Topics: [d-matrix](), [NVLink](), [Nvidia](), [xpu](), [AI Inference](), [datacenter](), [networking](), [cpu](), [Spectrum-X]() Tags: [accelerators](), [ai](), [ai-accelerator](), [ai-inference](), [d-matrix](), [data-center](), [ethernet](), [networking](), [nvidia](), [nvidia-vera](), [nvlink](), [server](), [xpu]() ### AI overview d-Matrix and NVIDIA announced that d-Matrix will bring its next-generation XPUs to the NVLink Fusion platform. The integration is intended to support scaling from individual Raptor XPUs to larger rack-scale and clustered deployments for AI inference, alongside NVIDIA networking and CPU technologies. ### Source excerpt d-Matrix and NVIDIA announced that d-Matrix will use NVLink Fusion to scale up and out with its next-gen Raptor AI accelerators The post d-Matrix Joins the NVIDIA NVLink Fusion Platform appeared first on ServeTheHome. ## Backblaze B2 and WEKA NeuralMesh Validated as a Two-Tier AI Storage Pipeline, With Snap-to-Object Checkpoints in B2 DevFeed: [Backblaze B2 and WEKA NeuralMesh Validated as a Two-Tier AI Storage Pipeline, With Snap-to-Object Checkpoints in B2]() Original publisher: [Read original article]() Author: Harold Fritts Published: 2026-09-10T20:40:57Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [AI Infrastructure](), [cloud-infrastructure](), [Cloud](), [data-processing](), [model-deployment]() Tags: [accelerators](), [ai](), [ai-infrastructure](), [cloud](), [cloud-storage](), [data](), [datasets](), [enterprise](), [inference](), [infrastructure](), [integration](), [performance](), [snapshots](), [storage]() ### AI overview Backblaze and WEKA validated a two-tier AI storage pipeline that uses WEKA NeuralMesh as the high-performance tier for GPU workloads and Backblaze B2 Cloud Storage as the capacity tier. Raw data, training sets, media, source files, checkpoints, and other assets can move between the tiers according to access needs. NeuralMesh's Snap-to-Object feature was also tested with B2 for storing consistent filesystem snapshots and supporting recovery. ### Source excerpt Backblaze and WEKA have validated their two platforms together for AI pipelines, pairing WEKA NeuralMesh as the performance tier that feeds GPUs with Backblaze B2 Cloud Storage as the capacity tier that holds everything else. The integration, sizing, tuning, and testing are already done, so an AI infrastructure team can deploy a proven two-tier layout The post Backblaze B2 and WEKA NeuralMesh Validated as a Two-Tier AI Storage Pipeline, With Snap-to-Object Checkpoints in B2 appeared first on StorageReview.com. ## AMD Reveals Threadripper Halo Station: 96 Cores and up to 576GB of HBM3E Aimed Straight at DGX Station DevFeed: [AMD Reveals Threadripper Halo Station: 96 Cores and up to 576GB of HBM3E Aimed Straight at DGX Station]() Original publisher: [Read original article]() Author: Brian Beeler Published: 2026-09-04T16:08:49Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [DGX Station](), [GPU](), [Nvidia](), [cpu](), [AI Models](), [Inference](), [Arm](), [toolchain]() Tags: [2026](), [accelerators](), [ai](), [ai-models](), [arm](), [consumer](), [cpu](), [dgx-station](), [gpu](), [toolchain](), [workstation]() ### AI overview AMD revealed the Threadripper Halo Station, a liquid-cooled workstation combining a 96-core Threadripper PRO CPU with two Instinct MI350P accelerators. AMD positions it as an answer to NVIDIA's GB300-based DGX Station, with up to four accelerators, 576GB of HBM3E, 2TB of DDR5 memory, and support for AI models exceeding one trillion parameters. The article contrasts AMD's expandable, discrete design with NVIDIA's unified-memory architecture. ### Source excerpt AMD used its IFA 2026 opening keynote to reveal the Threadripper Halo Station, a liquid-cooled workstation pairing a 96-core Threadripper PRO with a pair of Instinct MI350P accelerators, and the pitch could not be more direct: this is AMD's answer to NVIDIA's GB300 DGX Station. "This is the most powerful workstation in the world," said The post AMD Reveals Threadripper Halo Station: 96 Cores and up to 576GB of HBM3E Aimed Straight at DGX Station appeared first on StorageReview.com. ## Leveraging CPU memory for faster, cost-efficient TPU LLM training DevFeed: [Leveraging CPU memory for faster, cost-efficient TPU LLM training]() Original publisher: [Read original article]() Author: Google Open Source (noreply@blogger.com) Published: 2026-04-10T18:30:00Z Content type: tutorial Language: en Sources: [Google Open Source Blog]() Topics: [cpu](), [Large Language Model](), [intel](), [Google Cloud Platform (GCP)](), [Cloud](), [implementation]() Tags: [accelerators](), [cloud-tpu](), [cost](), [cpu](), [host-offloading](), [intel-xeon](), [jax](), [llm-training](), [memory](), [performance](), [tpu]() ### AI overview This practical guide explains how to use host activation offloading with JAX on TPU platforms. It describes moving selected activations from TPU device memory to Intel Xeon CPU memory to reduce accelerator memory pressure and support larger models or batch sizes, while discussing potential throughput and cost benefits. ### Source excerpt by Keyur Ruganathbhai Ranipa, Qinglan Xiang, Vrushabh Sanghavi, Ramesh AG & Weilin Wang, Intel and Penporn Koanantakool, Google Host offloading with JAX on Intel® Xeon® processors As Large Language Models (LLMs) continue to scale into the hundreds of billions of parameters, device memory capacity has become a big limiting factor in training, as intermediate activations from every layer in the forward pass are needed in the backward pass. To reduce device memory pressure, these activations can be rematerialized during the backward pass, trading memory for recomputation. While rematerialization enables larger models to fit within limited device memory, it significantly increases training time and cost. Intel® Xeon® processors (5th and 6th Gen) with Advanced Matrix Extensions (AMX) enable practical host offloading of selected memory- and compute-intensive components in JAX training workflows. This approach can help teams train larger models, relieve accelerator memory pressure, improve end-to-end throughput, and reduce total cost of ownership--particularly on TPU-based Google Cloud instances. By publishing these results and implementation details, Google and Intel aim to promote transparency and share practical guidance with the community. This post describes how to enable activation offloading for JAX on TPU platforms and outlines considerations for building scalable, cost-aware hybrid CPU-accelerator training workflows. Figure 1. Google Cloud TPU Pod commonly used in LLM training. Host offloading Traditional LLM training is usually done on device accelerators alone. However, modern host machines have much larger memory size than accelerators (512GB or more) and can offer extra compute power, e.g., TFLOPS in case of Intel® Xeon® Scalable Processor with AMX capability. Leveraging host resources can be a great alternative to rematerialization. Host offloading selectively moves computation or data between host and device to optimize performance and memory usage. Host memo ## Introducing HUGS - Scale your AI with Open Models DevFeed: [Introducing HUGS - Scale your AI with Open Models]() Original publisher: [Read original article]() Author: Philipp Schmid; Jeff Boudier; Alvaro Bartolome; Simon Pagezy; Violette Published: 2024-10-23T00:00:00Z Content type: article Language: en Sources: [Hugging Face - Blog]() Topics: [hugging face](), [model-deployment](), [tgi](), [Inference](), [Transformers](), [Open Source](), [Generative AI](), [Large Language Model](), [GPU](), [Microservices](), [API](), [Hardware]() Tags: [accelerate](), [accelerators](), [ai](), [ai-accelerator](), [amd](), [announcement](), [api](), [artificial-intelligence](), [aws](), [aws-inferentia](), [azure](), [digitalocean](), [enterprise](), [gcp](), [gpu](), [inference](), [llm](), [microservices](), [model-deployment](), [models](), [multimodal](), [open-source](), [partnerships](), [performance](), [technologies](), [text-generation](), [tgi](), [transformers]() ### AI overview Hugging Face introduces HUGS, optimized zero-configuration inference microservices for deploying open models in an organization's own infrastructure. Built on Hugging Face technologies including Text Generation Inference and Transformers, HUGS targets efficient, hardware-optimized deployment across NVIDIA and AMD GPUs, with AWS Inferentia and Google TPU support planned. It provides an OpenAI-compatible API and is designed to reduce deployment complexity and time for AI applications. ### Source excerpt We're on a journey to advance and democratize artificial intelligence through open source and open science. ## Accelerating Protein Language Model ProtST on Intel Gaudi 2 DevFeed: [Accelerating Protein Language Model ProtST on Intel Gaudi 2]() Original publisher: [Read original article]() Author: Julien Simon; Jiqing.Feng; Santiago Miret; Xinyu Yuan; Yi Wang; Matrix Yao; Minghao Xu; Ke Ding Published: 2024-07-03T00:00:00Z Content type: tutorial Language: en Sources: [Hugging Face - Blog]() Topics: [Large Language Model](), [Inference](), [Inference Performance](), [Fine-tuning](), [intel](), [Open Source](), [AI, ML & Data Engineering]() Tags: [accelerators](), [artificial-intelligence](), [batch](), [datasets](), [fine-tuning](), [hugging-face](), [inference](), [inference-performance](), [intel](), [language-models](), [llm](), [model](), [nvidia](), [optimum](), [partnerships](), [pcie](), [precision](), [transformers](), [zero-shot]() ### AI overview This tutorial explains how to run inference and fine-tune ProtST, a multimodal protein language model, using Intel Gaudi 2 accelerators and the Optimum for Intel Gaudi open-source library. It compares ProtST inference on NVIDIA A100 and Gaudi 2, reporting identical accuracy and 1.76x faster inference on Gaudi 2. ### Source excerpt We're on a journey to advance and democratize artificial intelligence through open source and open science. ## Mixed-input matrix multiplication performance optimizations DevFeed: [Mixed-input matrix multiplication performance optimizations]() Original publisher: [Read original article]() Author: Google AI (noreply@blogger.com) Published: 2024-01-26T19:56:00Z Content type: article Language: en Sources: [Google Research]() Topics: [Large language models (LLMs)](), [quantization](), [Hardware](), [GPU](), [Nvidia](), [Tensor Cores](), [Open Source](), [Software](), [data type]() Tags: [accelerators](), [ai](), [algorithms](), [ampere](), [compute](), [conversion](), [data](), [deep-learning](), [effective](), [efficiency](), [hardware](), [implementation](), [language-models](), [large-language-models-llms](), [models](), [nvidia](), [optimization](), [performance](), [precision](), [quantization](), [research](), [software](), [tensor-cores]() ### AI overview This Google Research article explains software techniques for mapping mixed-input matrix multiplication onto NVIDIA Ampere hardware. It describes using lower-precision weights with higher-precision inputs, data-type conversion, and layout transformations to support weight-only quantization. The authors report minimal software overhead and performance close to peak hardware capabilities, and state that the techniques were released in the open-source NVIDIA/CUTLASS repository. ### Source excerpt Posted by Manish Gupta, Staff Software Engineer, Google Research AI-driven technologies are weaving themselves into the fabric of our daily routines, with the potential to enhance our access to knowledge and boost our overall productivity. The backbone of these applications lies in large language models (LLMs). LLMs are memory-intensive and typically require specialized hardware accelerators to efficiently deliver tens of exaflops of computing power. This blog post shows how we can start addressing the computational challenges by utilizing memory more effectively. The bulk of an LLM's memory and compute are consumed by weights in matrix multiplication operations. Using narrower data types reduces memory consumption. For example, storing weights in the 8-bit integer (i.e., U8 or S8) data type reduces the memory footprint by 4x relative to single-precision (F32) and 2x relative to half-precision (F16) or bfloat16 (BF16). Furthermore, previous work has shown that LLM models running matrix multiplications with weights in S8 and input in F16 (preserving higher precision of the user-input) is an effective method for increasing the efficiency with acceptable trade-offs in accuracy. This technique is known as weight-only quantization and requires efficient implementation of matrix multiplication with mixed-inputs, e.g., half-precision input multiplied with 8-bits integer. Hardware accelerators, including GPUs, support a fixed set of data types, and thus, mixed-input matrix multiplication requires software transformations to map to the hardware operations. To that end, in this blog we focus on mapping mixed-input matrix multiplication onto the NVIDIA Ampere architecture. We present software techniques addressing data type conversion and layout conformance to map mixed-input matrix multiplication efficiently onto hardware-supported data types and layouts. Our results show that the overhead of additional work in software is minimal and enables performance close to the peak har ## New reference pages on MDN for JavaScript regular expressions DevFeed: [New reference pages on MDN for JavaScript regular expressions]() Original publisher: [Read original article]() Author: brian-smith Published: 2023-05-23T00:00:00Z Content type: article Language: en Sources: [MDN Blog]() Topics: [Regular expression](), [JavaScript](), [browser](), [Web Development]() Tags: [accelerators](), [browser](), [cheat-sheet](), [compatibility](), [docs](), [documentation](), [github](), [javascript](), [pull-request](), [search](), [updates]() ### AI overview MDN Web Docs has published 18 new reference pages for individual JavaScript regular-expression features. The pages provide more comprehensive syntax and semantics information, include browser compatibility details, remove deprecated content, and organize the material into sections such as flags, assertions, atoms, and other features. ### Source excerpt See the latest updates to the MDN reference pages about JavaScript regular expressions, including new sections on sub-features and browser compatibility information.