# AI/ML/DL Published articles for AI/ML/DL. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Agentic AI Automates Design-Rule Repair While Preserving Layout Equivalence (Purdue University) DevFeed: [Agentic AI Automates Design-Rule Repair While Preserving Layout Equivalence (Purdue University)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T20:01:40Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Artificial Intelligence](), [rule-engine](), [Inference](), [Language models](), [Large Language Model](), [LLM Techniques]() Tags: [agentic](), [agentic-ai](), [ai](), [ai-ml-dl](), [artificial-intelligence](), [automated-layout-repair](), [design-rule-checking](), [design-rule-violations](), [design-verification](), [drc](), [drc-aid](), [drv](), [eda](), [electronic-design-automation](), [engineering](), [inference](), [language-models](), [large-language-models](), [layout-versus-schematic](), [llm](), [lvs](), [paper](), [physical-design](), [physical-verification](), [purdue-university](), [rule-engine](), [semiconductor-research](), [siemens-calibre](), [technical-papers](), [university](), [verification](), [verification-in-the-loop]() ### AI overview A Purdue University technical paper presents DRC-Aid, a closed-loop agentic framework that uses inference-time large language models and verification-in-the-loop search to automate local design-rule correction. A deterministic rule engine constrains repairs to a bounded set of geometric edits. ### Source excerpt Researchers at Purdue University published a technical paper titled "DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models." Abstract Excerpt: "We present DRC-Aid, a closed-loop agentic framework that automates local DRC repair by formulating it as verification-in-the-loop search. To constrain the combinatorial geometric repair space, a deterministic Rule Engine converts physical verification tool-reported... " read more The post Agentic AI Automates Design-Rule Repair While Preserving Layout Equivalence (Purdue University) appeared first on Semiconductor Engineering. ## Reinforcement Learning Cuts Routing Violations in Dense Chip Layouts (NYU) DevFeed: [Reinforcement Learning Cuts Routing Violations in Dense Chip Layouts (NYU)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:54:29Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Reinforcement learning](), [Routing (disambiguation)](), [iteration]() Tags: [ai-ml-dl](), [artificial-intelligence](), [design-rule-violations](), [design-verification](), [detailed-routing](), [drv](), [eda](), [electronic-design-automation](), [long-short-term-memory](), [lstm](), [machine-learning](), [nyu](), [offline-reinforcement-learning](), [paper](), [physical-design](), [placement-density](), [recurrent-neural-networks](), [reinforcement-learning](), [rl](), [routing-optimization](), [semiconductor](), [semiconductor-research](), [technical-papers]() ### AI overview Researchers at New York University published a technical paper on using a history-aware offline reinforcement-learning policy with LSTM to predict routing cost weights and improve convergence in dense chip layouts. ### Source excerpt Researchers at New York University published a technical paper titled "Routing Dense Layouts with History-Aware Offline Reinforcement Learning using LSTM." Abstract Excerpt: "Detailed routing remains a dominant runtime bottleneck in physical design due to increasing complexity of design rules. Modern routers can struggle to resolve persistent violations under dense operating conditions. While recent work leverages... " read more The post Reinforcement Learning Cuts Routing Violations in Dense Chip Layouts (NYU) appeared first on Semiconductor Engineering. ## Chiplet Co-Design Framework Reduces Energy and Design Costs for AI Accelerators (University of Michigan) DevFeed: [Chiplet Co-Design Framework Reduces Energy and Design Costs for AI Accelerators (University of Michigan)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:44:42Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Artificial Intelligence](), [Neural Network](), [circuit]() Tags: [2026](), [accelerator-co-design](), [ai](), [ai-accelerators](), [ai-ml-dl](), [architectures](), [automotive-aerospace](), [chiplet-ecosystem](), [chiplets](), [circuit](), [design-space-exploration](), [ecosystem](), [energy-efficiency](), [engineering](), [fengshui](), [hardware-software-co-design](), [heterogeneous-integration](), [llm-inference](), [memory-hierarchy](), [mixture-of-experts](), [moe](), [neural-network](), [neural-networks](), [paper](), [physical-design](), [pim](), [power-and-performance](), [power-performance](), [processing-in-memory](), [semiconductor](), [september-2026](), [technical](), [technical-papers](), [university](), [university-of-michigan]() ### AI overview Researchers at the University of Michigan published a technical paper introducing Fengshui, a chiplet ecosystem and accelerator co-design framework. The framework jointly optimizes chiplet pool composition and bespoke application-specific integrated circuit design for neural network accelerators. ### Source excerpt Researchers at the University of Michigan published a technical paper titled "Fengshui: Demystifying Chiplet Ecosystem and Bespoke Neural Network Accelerator Codesign." Abstract Excerpt: "This paper introduces Fengshui, a chiplet ecosystem and accelerator co-design framework that jointly optimizes chiplet pool composition and bespoke application-specific integrated circuit (BASIC) design." Find the technical paper here. September 2026. Jin,... " read more The post Chiplet Co-Design Framework Reduces Energy and Design Costs for AI Accelerators (University of Michigan) appeared first on Semiconductor Engineering. ## Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech) DevFeed: [Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:37:45Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Benchmark](), [Artificial Intelligence](), [3D]() Tags: [2-5d-ic](), [3d](), [3d-ic](), [advanced-packaging](), [ai](), [ai-for-eda](), [ai-ml-dl](), [benchmark](), [chiplets](), [design-verification](), [engineering](), [ic-thermbench](), [machine-learning](), [ood](), [out-of-distribution-generalization](), [packaging](), [paper](), [power-performance](), [semiconductor](), [shanghaitech-university](), [technical-papers](), [technical-university-of-munich](), [thermal-management](), [thermal-modeling](), [thermal-prediction](), [thermal-simulation](), [university-of-technology-sydney]() ### AI overview Researchers from the University of Technology Sydney, ShanghaiTech University, and Technical University of Munich published IC-ThermBench, an open benchmark for evaluating generalizable AI models for thermal behavior in 2.5D and 3D integrated circuits. The benchmark includes steady-state, transient, industrial package, and 2.5D chiplet tasks, including a 50,000-sample extension. ### Source excerpt Researchers at the University of Technology Sydney, ShanghaiTech University, and Technical University of Munich published a technical paper titled "IC-ThermBench: An Open, Progressive Benchmark for Generalizable 2.5D/3D-IC Thermal Learning." Abstract Excerpt: "We introduce IC-ThermBench, an open and progressive benchmark that combines established 3D-IC steady-state, transient, and industrial package tasks with a new 50,000-sample 2.5D chiplet... " read more The post Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech) appeared first on Semiconductor Engineering. ## AI in Chip Design: From Code Generation to EDA Orchestration (University of Edinburgh) DevFeed: [AI in Chip Design: From Code Generation to EDA Orchestration (University of Edinburgh)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:30:22Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Artificial Intelligence](), [Chip design](), [Orchestration](), [Code generation]() Tags: [agentic-ai](), [ai](), [ai-agents](), [ai-ml-dl](), [artificial-intelligence](), [chip](), [chip-design](), [code-generation](), [design-automation](), [design-verification](), [eda](), [eda-orchestration](), [electronic-design-automation](), [generative-ai](), [hardware-design](), [large-language-models](), [llm](), [rtl-generation](), [synthesis](), [technical-papers](), [university](), [university-of-edinburgh](), [verification]() ### AI overview Researchers at the University of Edinburgh examine how large language models could support digital electronic design automation, comparing generator, agent, and orchestrator roles. The perspective highlights challenges including plausible but physically incorrect code, fragmented tools, and loss of design context, and proposes physics-aware orchestration for more reliable hardware design. ### Source excerpt Researchers at the University of Edinburgh published a technical perspective titled "LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration." Abstract Excerpt: "In this Perspective, we instead define three hierarchical roles that reveal how capability accumulates: a Generator that produces design artifacts in a single pass, an Agent that refines outputs... " read more The post AI in Chip Design: From Code Generation to EDA Orchestration (University of Edinburgh) appeared first on Semiconductor Engineering. ## Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University) DevFeed: [Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:23:56Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Computing](), [Scalability](), [systems](), [Network]() Tags: [2026](), [2d-mesh](), [ai-ml-dl](), [analog](), [architecture](), [architectures](), [arq](), [automatic-repeat-request](), [brainscales](), [brainscales-2](), [chiplet-interconnects](), [chiplets](), [computing](), [cost](), [credit-based-flow-control](), [data](), [data-movement](), [die-to-die-communication](), [engineering](), [error-control](), [flexibility](), [heidelberg-university](), [implementing](), [mixed-signal-circuits](), [network](), [neuromorphic](), [neuromorphic-computing](), [packaging](), [paper](), [routing-chiplets](), [scaling](), [semiconductor](), [snn](), [spiking-neural-networks](), [system](), [systems](), [technical-papers]() ### AI overview Researchers at Heidelberg University describe a unified interconnection network for scaling the BrainScaleS-2 neuromorphic system with chiplet-based designs. The proposed routing chiplet connects multiple units in a 2D mesh and handles both error-tolerant spike traffic and error-intolerant configuration and processing-unit data. ### Source excerpt Researchers at Heidelberg University published a technical paper titled "A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System." Abstract Excerpt: "To overcome the challenges of scaling analog designs, chiplet-based designs offer a promising approach with cost and flexibility advantages over monolithic scaling. Implementing a chiplet-based BSS-2* architecture requires an interconnection network that... " read more The post Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University) appeared first on Semiconductor Engineering.