# air-gap isolation

Published articles for air-gap isolation.

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## Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.)

DevFeed: [Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.)](<https://devfeed.tech/articles/wafer-scale-sub-5nm-channel-monolayer-mos2-transistors-cmu-uf-mit-et-al-57976.md>)

Original publisher: [Read original article](<https://semiengineering.com/wafer-scale-sub-5nm-channel-monolayer-mos2-transistors-cmu-uf-mit-et-al/>)

Author: Technical Paper Link

Published: 2026-09-22T17:51:42Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [The Chapel Parallel Programming Language](<https://devfeed.tech/topics/chapel.md>), [Chip design](<https://devfeed.tech/topics/chip-design.md>)

Tags: [2d-semiconductors](<https://devfeed.tech/tags/2d-semiconductors.md>), [advanced-process-nodes](<https://devfeed.tech/tags/advanced-process-nodes.md>), [air-gap-isolation](<https://devfeed.tech/tags/air-gap-isolation.md>), [carnegie-mellon-university](<https://devfeed.tech/tags/carnegie-mellon-university.md>), [cmos-compatible-processing](<https://devfeed.tech/tags/cmos-compatible-processing.md>), [manufacturing](<https://devfeed.tech/tags/manufacturing.md>), [materials](<https://devfeed.tech/tags/materials.md>), [mit](<https://devfeed.tech/tags/mit.md>), [molybdenum-disulfide](<https://devfeed.tech/tags/molybdenum-disulfide.md>), [photolithography](<https://devfeed.tech/tags/photolithography.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [short-channel-effects](<https://devfeed.tech/tags/short-channel-effects.md>), [silicon](<https://devfeed.tech/tags/silicon.md>), [sub-5nm](<https://devfeed.tech/tags/sub-5nm.md>), [subthreshold-swing](<https://devfeed.tech/tags/subthreshold-swing.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [texas-a-m-university](<https://devfeed.tech/tags/texas-a-m-university.md>), [transistor-scaling](<https://devfeed.tech/tags/transistor-scaling.md>), [transistors](<https://devfeed.tech/tags/transistors.md>), [universidad-politecnica-de-madrid](<https://devfeed.tech/tags/universidad-politecnica-de-madrid.md>), [university-of-florida](<https://devfeed.tech/tags/university-of-florida.md>), [university-of-southern-california](<https://devfeed.tech/tags/university-of-southern-california.md>), [wafer-scale-integration](<https://devfeed.tech/tags/wafer-scale-integration.md>)

### AI overview

Researchers report monolayer MoS₂ transistors with channel lengths below 5 nm, a subthreshold swing of 88 mV/dec, and an on/off ratio above 10⁶. They describe a photolithography-based, CMOS-compatible process and demonstrate integration across a 4-inch wafer.

### Source excerpt

Researchers at Carnegie Mellon University, University of Florida, MIT, Texas A&M University et al. published a technical paper titled "Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit." Abstract Excerpt "Here, we report monolayer MoS₂ transistors with physical channel lengths below 5 nm, achieving a subthreshold swing of 88 mV/dec... " read more The post Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.) appeared first on Semiconductor Engineering.