# AVX

Published articles for AVX.

This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles.

## Ubuntu 26.10 amd64v3 Performance Compared with Generic amd64 on Budget Hardware

DevFeed: [Ubuntu 26.10 amd64v3 Performance Compared with Generic amd64 on Budget Hardware](<https://devfeed.tech/articles/ubuntu-26-10-amd64v3-can-provide-a-nice-boost-for-low-end-budget-hardware-31413.md>)

Original publisher: [Read original article](<https://www.phoronix.com/review/ubuntu-2610-amd64v3-lowend>)

Author: Michael Larabel

Published: 2026-09-16T17:37:00Z

Content type: article

Language: en

Sources: [Phoronix](<https://devfeed.tech/sources/phoronix.md>)

Topics: [Ubuntu](<https://devfeed.tech/topics/ubuntu.md>), [canonical](<https://devfeed.tech/topics/canonical.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [Intel Core](<https://devfeed.tech/topics/intel-core.md>), [x86](<https://devfeed.tech/topics/x86.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [benchmarks](<https://devfeed.tech/tags/benchmarks.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [desktop-linux](<https://devfeed.tech/tags/desktop-linux.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [intel-core](<https://devfeed.tech/tags/intel-core.md>), [linux-benchmarking](<https://devfeed.tech/tags/linux-benchmarking.md>), [linux-hardware-benchmarks](<https://devfeed.tech/tags/linux-hardware-benchmarks.md>), [linux-hardware-reviews](<https://devfeed.tech/tags/linux-hardware-reviews.md>), [linux-how-to](<https://devfeed.tech/tags/linux-how-to.md>), [linux-performance](<https://devfeed.tech/tags/linux-performance.md>), [linux-server-benchmarks](<https://devfeed.tech/tags/linux-server-benchmarks.md>), [open-source-graphics](<https://devfeed.tech/tags/open-source-graphics.md>), [phoronix](<https://devfeed.tech/tags/phoronix.md>), [phoronix-test-suite](<https://devfeed.tech/tags/phoronix-test-suite.md>), [release](<https://devfeed.tech/tags/release.md>), [ubuntu](<https://devfeed.tech/tags/ubuntu.md>), [ubuntu-benchmarks](<https://devfeed.tech/tags/ubuntu-benchmarks.md>), [ubuntu-hardware](<https://devfeed.tech/tags/ubuntu-hardware.md>), [wildcat-lake](<https://devfeed.tech/tags/wildcat-lake.md>), [x86-64-v3](<https://devfeed.tech/tags/x86-64-v3.md>)

### AI overview

This Phoronix review compares Ubuntu 26.10 amd64 and amd64v3 daily builds on the same entry-level CHUWI UniBook laptop with an Intel Core 3 304 processor and 8GB of RAM. It examines whether amd64v3 binaries improve performance on budget hardware, while noting that Canonical's official plans for Ubuntu 26.10 amd64v3 were not yet known.

### Source excerpt

Canonical recently began producing Ubuntu 26.10 amd64v3 daily ISOs to complement their experimental amd64v3 package archive that they have been trialing the past few release cycles. While we still don't know what any official plans are for amd64v3 with Ubuntu 26.10, the performance gains can be very worthwhile over the generic amd64 binaries even for low-end/budget hardware.

## OpenVDB Introduces SIMD Framework With Some 2~4x Performance Improvements

DevFeed: [OpenVDB Introduces SIMD Framework With Some 2~4x Performance Improvements](<https://devfeed.tech/articles/openvdb-introduces-simd-framework-with-some-2-4x-performance-improvements-31411.md>)

Original publisher: [Read original article](<https://www.phoronix.com/news/OpenVDB-SIMD--Framework>)

Author: Michael Larabel

Published: 2026-09-16T10:05:23Z

Content type: news

Language: en

Sources: [Phoronix](<https://devfeed.tech/sources/phoronix.md>)

Topics: [Data structures](<https://devfeed.tech/topics/data-structures.md>), [Tooling](<https://devfeed.tech/topics/tooling.md>), [x86](<https://devfeed.tech/topics/x86.md>), [releases](<https://devfeed.tech/topics/releases.md>), [cudnn](<https://devfeed.tech/topics/cudnn.md>), [Open Source](<https://devfeed.tech/topics/open-source.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [command-line](<https://devfeed.tech/tags/command-line.md>), [cuda](<https://devfeed.tech/tags/cuda.md>), [data](<https://devfeed.tech/tags/data.md>), [data-structure](<https://devfeed.tech/tags/data-structure.md>), [desktop-linux](<https://devfeed.tech/tags/desktop-linux.md>), [github](<https://devfeed.tech/tags/github.md>), [kernels](<https://devfeed.tech/tags/kernels.md>), [linux-benchmarking](<https://devfeed.tech/tags/linux-benchmarking.md>), [linux-hardware-benchmarks](<https://devfeed.tech/tags/linux-hardware-benchmarks.md>), [linux-hardware-reviews](<https://devfeed.tech/tags/linux-hardware-reviews.md>), [linux-how-to](<https://devfeed.tech/tags/linux-how-to.md>), [linux-performance](<https://devfeed.tech/tags/linux-performance.md>), [linux-server-benchmarks](<https://devfeed.tech/tags/linux-server-benchmarks.md>), [open-source-graphics](<https://devfeed.tech/tags/open-source-graphics.md>), [performance](<https://devfeed.tech/tags/performance.md>), [phoronix](<https://devfeed.tech/tags/phoronix.md>), [phoronix-test-suite](<https://devfeed.tech/tags/phoronix-test-suite.md>), [release](<https://devfeed.tech/tags/release.md>), [ubuntu-benchmarks](<https://devfeed.tech/tags/ubuntu-benchmarks.md>), [ubuntu-hardware](<https://devfeed.tech/tags/ubuntu-hardware.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

OpenVDB 13.1 introduces a SIMD framework using Agner Fog's VectorClass Library for explicit x86 vectorization up to AVX-512. Adapted point transfer algorithms reportedly achieve 2x to 4x performance improvements on modern AVX-512 x86_64 CPUs. The release also includes NanoVDB CUDA resource-management and kernel improvements, plus updates to vdb_tool.

### Source excerpt

OpenVDB is the sparse volume data structure and tooling library maintained by the Academy Software Foundation. OpenVDB in turn is used by various CGI software for dealing with sparse volumetric data such as Houdini, RenderMan, and Cinema 4D to the open-source Blender. It's even won an Academy Award for technical achievement while now in 2026 it's finally establishing a SIMD framework for better leveraging modern x86 ISA capabilities...

## Parsing common IPv4 addresses in C# with AVX-512

DevFeed: [Parsing common IPv4 addresses in C# with AVX-512](<https://devfeed.tech/articles/parsing-ip-addresses-in-c-at-crazy-speeds-29423.md>)

Original publisher: [Read original article](<https://lemire.me/blog/2026/08/19/parsing-ip-addresses-in-c-at-crazy-speeds/>)

Author: Daniel Lemire

Published: 2026-08-19T19:07:48Z

Content type: article

Language: en

Sources: [Daniel Lemire](<https://devfeed.tech/sources/daniel-lemire.md>)

Topics: [C#](<https://devfeed.tech/topics/csharp.md>), [Parsing](<https://devfeed.tech/topics/parsing.md>), [performance-optimization](<https://devfeed.tech/topics/performance-optimization.md>), [.NET](<https://devfeed.tech/topics/net.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [c-sharp](<https://devfeed.tech/tags/c-sharp.md>), [ip](<https://devfeed.tech/tags/ip.md>), [ipv4](<https://devfeed.tech/tags/ipv4.md>), [parsing](<https://devfeed.tech/tags/parsing.md>), [performance](<https://devfeed.tech/tags/performance.md>)

### AI overview

The article examines parsing common IPv4 address strings in C# for performance. It discusses using SIMD and AVX-512 support in .NET 10, including masked loads for safely loading strings shorter than a SIMD register width.

### Source excerpt

We are all familiar with IP addresses such as 192.168.0.1. They are typically written as four numbers in the range 0 to 255 inclusive, separated by dots. In C#, you can parse them with the standard library using IPAddress.TryParse. Pedantic people are quick to point out that IP addresses can take different forms: they can ... Continue reading Parsing IP addresses in C# at crazy speeds

## How much do amd64 microarchitecture levels help in Go?

DevFeed: [How much do amd64 microarchitecture levels help in Go?](<https://devfeed.tech/articles/how-much-do-amd64-microarchitecture-levels-help-in-go-29410.md>)

Original publisher: [Read original article](<https://lemire.me/blog/2026/06/06/how-much-do-amd64-microarchitecture-levels-help-in-go/>)

Author: Daniel Lemire

Published: 2026-06-06T20:25:19Z

Content type: article

Language: en

Sources: [Daniel Lemire](<https://devfeed.tech/sources/daniel-lemire.md>)

Topics: [Go Language](<https://devfeed.tech/topics/go-language.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [Data structures](<https://devfeed.tech/topics/data-structures.md>), [toolchain](<https://devfeed.tech/topics/toolchain.md>), [intel](<https://devfeed.tech/topics/intel.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [benchmark](<https://devfeed.tech/tags/benchmark.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [data-structure](<https://devfeed.tech/tags/data-structure.md>), [go](<https://devfeed.tech/tags/go.md>), [intel](<https://devfeed.tech/tags/intel.md>), [performance](<https://devfeed.tech/tags/performance.md>), [toolchain](<https://devfeed.tech/tags/toolchain.md>)

### AI overview

This article examines how amd64 microarchitecture levels affect Go program performance. It explains the instruction-set levels and reports a benchmark methodology using the Roaring Bitmaps library on an Intel Xeon Gold 6548N with Go 1.26.2 and Roaring v2.18.2. The supplied text does not include the benchmark results.

### Source excerpt

Our 64-bit Intel and AMD processors have evolved over decades. When you compile a Go program for a 64-bit Intel or AMD processor, the compiler targets, by default, a nearly 20-year-old instruction set. The binary that comes out runs on essentially any x64 chip, but it also leaves on the table every instruction that was ... Continue reading How much do amd64 microarchitecture levels help in Go?

## Parsing IPv6 Addresses with AVX-512

DevFeed: [Parsing IPv6 Addresses with AVX-512](<https://devfeed.tech/articles/parsing-ipv6-addresses-crazily-fast-with-avx-512-29408.md>)

Original publisher: [Read original article](<https://lemire.me/blog/2026/05/23/parsing-ipv6-addresses-crazily-fast-with-avx-512/>)

Author: Daniel Lemire

Published: 2026-05-23T02:45:11Z

Content type: article

Language: en

Sources: [Daniel Lemire](<https://devfeed.tech/sources/daniel-lemire.md>)

Topics: [Parsing](<https://devfeed.tech/topics/parsing.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [Internet](<https://devfeed.tech/topics/internet.md>)

Tags: [amd](<https://devfeed.tech/tags/amd.md>), [avx](<https://devfeed.tech/tags/avx.md>), [benchmark](<https://devfeed.tech/tags/benchmark.md>), [intel](<https://devfeed.tech/tags/intel.md>), [internet](<https://devfeed.tech/tags/internet.md>), [ipv6](<https://devfeed.tech/tags/ipv6.md>), [parsing](<https://devfeed.tech/tags/parsing.md>)

### AI overview

This article explains how an AVX-512 implementation parses IPv6 addresses using SIMD operations. The approach loads the input into a 512-bit register, identifies colons, expands bytes, translates hexadecimal digits, and combines them into bytes with few branches. It also describes a benchmark using randomly generated canonical compressed IPv6 addresses, but the supplied text does not include benchmark results.

### Source excerpt

Every machine connected to the Internet has an address called an IP address. Originally, these addresses were 32-bit integers (IPv4), giving a theoretical maximum of about four billion distinct addresses. We are all familiar with these addresses (e.g., 192.168.0.0). There was a big fuss about how we would run out of addresses. It never happened ... Continue reading Parsing IPv6 Addresses Crazily Fast with AVX-512

## SIMD-accelerated integer-to-string conversion

DevFeed: [SIMD-accelerated integer-to-string conversion](<https://devfeed.tech/articles/simd-accelerated-integer-to-string-conversion-29406.md>)

Original publisher: [Read original article](<https://lemire.me/blog/2026/05/18/simd-accelerated-integer-to-string-conversion/>)

Author: Daniel Lemire

Published: 2026-05-18T19:39:49Z

Content type: article

Language: en

Sources: [Daniel Lemire](<https://devfeed.tech/sources/daniel-lemire.md>)

Topics: [C++](<https://devfeed.tech/topics/c-plus-plus.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [Compiler](<https://devfeed.tech/topics/compiler.md>), [Logging](<https://devfeed.tech/topics/logging.md>)

Tags: [amd](<https://devfeed.tech/tags/amd.md>), [avx](<https://devfeed.tech/tags/avx.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [compiler](<https://devfeed.tech/tags/compiler.md>), [csv](<https://devfeed.tech/tags/csv.md>), [intel](<https://devfeed.tech/tags/intel.md>), [json](<https://devfeed.tech/tags/json.md>), [logging](<https://devfeed.tech/tags/logging.md>), [performance](<https://devfeed.tech/tags/performance.md>)

### AI overview

This article explains SIMD-based techniques for converting 64-bit integers to decimal strings. It describes division and lookup-table approaches, then discusses using AVX-512 and IFMA instructions on recent AMD and Intel processors to process multiple values in parallel.

### Source excerpt

Converting a 64-bit integer to its decimal string representation is a mundane task that shows up everywhere: logging, JSON serialization, CSV output, debug prints, etc. In C++, you might use std::to_chars, sprintf, or some library routine. How do these functions work? At a high level, they repeatedly divide by ten. Start with your integer k. ... Continue reading SIMD-accelerated integer-to-string conversion

## Matching JSON and whitespace characters efficiently on ARM processors

DevFeed: [Matching JSON and whitespace characters efficiently on ARM processors](<https://devfeed.tech/articles/the-fastest-way-to-match-characters-on-arm-processors-29401.md>)

Original publisher: [Read original article](<https://lemire.me/blog/2026/04/19/the-fastest-way-to-match-characters-on-arm-processors/>)

Author: Daniel Lemire

Published: 2026-04-19T20:41:04Z

Content type: article

Language: en

Sources: [Daniel Lemire](<https://devfeed.tech/sources/daniel-lemire.md>)

Topics: [Arm](<https://devfeed.tech/topics/arm.md>), [JSON](<https://devfeed.tech/topics/json.md>), [Parsing](<https://devfeed.tech/topics/parsing.md>)

Tags: [amd](<https://devfeed.tech/tags/amd.md>), [architecture](<https://devfeed.tech/tags/architecture.md>), [arm](<https://devfeed.tech/tags/arm.md>), [ascii](<https://devfeed.tech/tags/ascii.md>), [avx](<https://devfeed.tech/tags/avx.md>), [intel](<https://devfeed.tech/tags/intel.md>), [json](<https://devfeed.tech/tags/json.md>), [parsing](<https://devfeed.tech/tags/parsing.md>), [processors](<https://devfeed.tech/tags/processors.md>)

### AI overview

The article examines vectorized classification for matching ASCII whitespace and structural JSON characters. It describes a branch-free NEON approach and discusses newer ARM Scalable Vector Extension instructions as an alternative on recent ARM processors.

### Source excerpt

Consider the following problem. Given a string, you must match all of the ASCII white-space characters (\t, \n, \r, and the space) and some characters important in JSON (:, ,, [, ], {, }). JSON is a text-based data format used for web services. A toy JSON document looks as follows. { "name": "Alice", "age": ... Continue reading The fastest way to match characters on ARM processors?

## Ubuntu variant optimized with x86-64-v3

DevFeed: [Ubuntu variant optimized with x86-64-v3](<https://devfeed.tech/articles/ubuntu-variant-optimized-with-x86-64-v3-27746.md>)

Original publisher: [Read original article](<https://gagor.pro/2026/04/ubuntu-variant-optimized-with-x86-64-v3/>)

Author: Tom

Published: 2026-04-04T00:00:00Z

Content type: tutorial

Language: en

Sources: [Tomasz Gągor](<https://devfeed.tech/sources/tomasz-gagor.md>)

Topics: [Ubuntu](<https://devfeed.tech/topics/ubuntu.md>), [x86](<https://devfeed.tech/topics/x86.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [Linux](<https://devfeed.tech/topics/linux.md>)

Tags: [amd64v3](<https://devfeed.tech/tags/amd64v3.md>), [apt-configuration](<https://devfeed.tech/tags/apt-configuration.md>), [avx](<https://devfeed.tech/tags/avx.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [cpu-optimization](<https://devfeed.tech/tags/cpu-optimization.md>), [linux](<https://devfeed.tech/tags/linux.md>), [linux-performance](<https://devfeed.tech/tags/linux-performance.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [sse](<https://devfeed.tech/tags/sse.md>), [ubuntu](<https://devfeed.tech/tags/ubuntu.md>), [ubuntu-25-10](<https://devfeed.tech/tags/ubuntu-25-10.md>), [ubuntu-26-04](<https://devfeed.tech/tags/ubuntu-26-04.md>), [x86-64](<https://devfeed.tech/tags/x86-64.md>), [x86-64-v3](<https://devfeed.tech/tags/x86-64-v3.md>)

### AI overview

This tutorial explains Ubuntu's x86-64-v3 optimized package variant, including its rationale, compatibility considerations, and availability for testing in Ubuntu 25.10. It also discusses plans to extend the approach to Ubuntu 26.04 LTS.

### Source excerpt

Explore how to enable and use the x86-64-v3 optimized Ubuntu variant for better performance on modern hardware without sacrificing stability.

## Underrust: Multiple Return Values

DevFeed: [Underrust: Multiple Return Values](<https://devfeed.tech/articles/underrust-multiple-return-values-35460.md>)

Original publisher: [Read original article](<https://darkcoding.net/software/rust-multiple-return-types/>)

Author: Graham King

Published: 2022-10-18T07:00:00Z

Content type: tutorial

Language: en

Sources: [Graham King](<https://devfeed.tech/sources/graham-king.md>)

Topics: [Rust](<https://devfeed.tech/topics/rust.md>), [Assembly](<https://devfeed.tech/topics/assembly.md>), [LLVM](<https://devfeed.tech/topics/llvm.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>)

Tags: [assembly](<https://devfeed.tech/tags/assembly.md>), [avx](<https://devfeed.tech/tags/avx.md>), [llvm](<https://devfeed.tech/tags/llvm.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [rust](<https://devfeed.tech/tags/rust.md>), [simd](<https://devfeed.tech/tags/simd.md>), [software](<https://devfeed.tech/tags/software.md>), [underrust](<https://devfeed.tech/tags/underrust.md>)

### AI overview

This article examines how Rust returns values at the ABI and assembly levels. It covers integer and floating-point returns, multiple values, structs, function pointers, caller-stack returns, return-value optimization, and an LLVM SIMD optimization using AVX registers.

### Source excerpt

How does Rust return values, and does it make any difference to us programmers?

## Overthinking Leetcode's Two Sum with SIMD

DevFeed: [Overthinking Leetcode's Two Sum with SIMD](<https://devfeed.tech/articles/overthinking-leetcode-s-two-sum-with-simd-35478.md>)

Original publisher: [Read original article](<https://darkcoding.net/software/two-sum/>)

Author: Graham King

Published: 2022-10-09T07:00:00Z

Content type: tutorial

Language: en

Sources: [Graham King](<https://devfeed.tech/sources/graham-king.md>)

Topics: [Algorithms](<https://devfeed.tech/topics/algorithms.md>), [Code](<https://devfeed.tech/topics/code.md>), [Rust](<https://devfeed.tech/topics/rust.md>)

Tags: [algorithm](<https://devfeed.tech/tags/algorithm.md>), [algorithms](<https://devfeed.tech/tags/algorithms.md>), [array](<https://devfeed.tech/tags/array.md>), [avx](<https://devfeed.tech/tags/avx.md>), [benchmarks](<https://devfeed.tech/tags/benchmarks.md>), [code](<https://devfeed.tech/tags/code.md>), [complexity](<https://devfeed.tech/tags/complexity.md>), [interview](<https://devfeed.tech/tags/interview.md>), [performance](<https://devfeed.tech/tags/performance.md>), [rust](<https://devfeed.tech/tags/rust.md>), [simd](<https://devfeed.tech/tags/simd.md>), [software](<https://devfeed.tech/tags/software.md>)

### AI overview

This article examines the Two Sum problem by comparing a brute-force linear scan with a map-based solution. It discusses their complexity, implementation costs, and when the linear approach may be faster, including the possibility of using AVX-512 instructions.

### Source excerpt

When is the linear scan Two Sum solution faster than a map? What if we use AVX-512 instructions?

## Ice Lake AVX-512 Downclocking

DevFeed: [Ice Lake AVX-512 Downclocking](<https://devfeed.tech/articles/ice-lake-avx-512-downclocking-28490.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-08-19T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [intel](<https://devfeed.tech/topics/intel.md>), [floating-point](<https://devfeed.tech/topics/floating-point.md>), [Rocket](<https://devfeed.tech/topics/rocket.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [avx512](<https://devfeed.tech/tags/avx512.md>), [blog](<https://devfeed.tech/tags/blog.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [floating-point](<https://devfeed.tech/tags/floating-point.md>), [icelake](<https://devfeed.tech/tags/icelake.md>), [intel](<https://devfeed.tech/tags/intel.md>), [performance](<https://devfeed.tech/tags/performance.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This technical post investigates AVX2- and AVX-512-related license-based downclocking on Intel Ice Lake and Rocket Lake CPUs. Measurements from an Ice Lake i5-1035G4 indicate little frequency reduction from wider instructions, with a reported 100 MHz decrease in one single-core case.

### Source excerpt

Examining the extent of AVX related downclocking on Intel's Ice Lake CPU

## AVX-512 Mask Registers, Again

DevFeed: [AVX-512 Mask Registers, Again](<https://devfeed.tech/articles/avx-512-mask-registers-again-28488.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/05/26/kreg2.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-05-26T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [intel](<https://devfeed.tech/topics/intel.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [avx512](<https://devfeed.tech/tags/avx512.md>), [blog](<https://devfeed.tech/tags/blog.md>), [compare](<https://devfeed.tech/tags/compare.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [vector](<https://devfeed.tech/tags/vector.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

The article revisits AVX-512 mask registers by examining an SKX processor die shot. It uses visual comparisons of register-file layouts and related processor dies to investigate whether a highlighted mystery block is the physical mask-register file.

### Source excerpt

Taking a second look at the newly introduced mask registers, this time with the benefit of a SKX die shot from Fritzchens Fritz.

## Ice Lake Store Elimination

DevFeed: [Ice Lake Store Elimination](<https://devfeed.tech/articles/ice-lake-store-elimination-28487.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/05/18/icelake-zero-opt.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-05-18T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [intel](<https://devfeed.tech/topics/intel.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [x86](<https://devfeed.tech/topics/x86.md>), [Compiler](<https://devfeed.tech/topics/compiler.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>)

Tags: [analysis](<https://devfeed.tech/tags/analysis.md>), [avx](<https://devfeed.tech/tags/avx.md>), [blog](<https://devfeed.tech/tags/blog.md>), [compiler](<https://devfeed.tech/tags/compiler.md>), [icelake](<https://devfeed.tech/tags/icelake.md>), [intel](<https://devfeed.tech/tags/intel.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This article analyzes zero-store optimization on Intel's Ice Lake architecture. It compares performance results across memory regions and examines how compiler-generated 512-bit versus 256-bit instructions, including AVX-512 clocking effects, influence the observed behavior.

### Source excerpt

We look at the zero store optimization as it applies to Intel's newest micro-architecture.

## Investigating AVX-512 Frequency Transitions on Intel CPUs

DevFeed: [Investigating AVX-512 Frequency Transitions on Intel CPUs](<https://devfeed.tech/articles/gathering-intel-on-intel-avx-512-transitions-28483.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-01-17T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [intel](<https://devfeed.tech/topics/intel.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [Linux](<https://devfeed.tech/topics/linux.md>), [Code](<https://devfeed.tech/topics/code.md>), [Script](<https://devfeed.tech/topics/script.md>), [Scripting](<https://devfeed.tech/topics/scripting.md>), [Shell](<https://devfeed.tech/topics/shell.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [benchmark](<https://devfeed.tech/tags/benchmark.md>), [blog](<https://devfeed.tech/tags/blog.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [code](<https://devfeed.tech/tags/code.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [linux](<https://devfeed.tech/tags/linux.md>), [metrics](<https://devfeed.tech/tags/metrics.md>), [performance](<https://devfeed.tech/tags/performance.md>), [python](<https://devfeed.tech/tags/python.md>), [scripting](<https://devfeed.tech/tags/scripting.md>), [shell](<https://devfeed.tech/tags/shell.md>), [tests](<https://devfeed.tech/tags/tests.md>), [uarch](<https://devfeed.tech/tags/uarch.md>)

### AI overview

This article investigates the detailed behavior of AVX and AVX-512 frequency transitions on Intel CPUs using target tests and sampled performance metrics. It describes the test structure and provides accompanying source code and data-generation scripts.

### Source excerpt

Investigating some details of SIMD related frequency transitions on Intel CPUs.

## A Note on Mask Registers

DevFeed: [A Note on Mask Registers](<https://devfeed.tech/articles/a-note-on-mask-registers-28482.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2019/12/05/kreg-facts.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2019-12-05T16:30:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [Hardware](<https://devfeed.tech/topics/hardware.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [intel](<https://devfeed.tech/topics/intel.md>), [Cache](<https://devfeed.tech/topics/cache.md>)

Tags: [architecture](<https://devfeed.tech/tags/architecture.md>), [avx](<https://devfeed.tech/tags/avx.md>), [blog](<https://devfeed.tech/tags/blog.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [cache](<https://devfeed.tech/tags/cache.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [execution](<https://devfeed.tech/tags/execution.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [intel](<https://devfeed.tech/tags/intel.md>), [performance](<https://devfeed.tech/tags/performance.md>), [uarch](<https://devfeed.tech/tags/uarch.md>)

### AI overview

This article examines AVX-512 mask registers and investigates the size of their physical register file using an updated out-of-order CPU resource probing tool. It explains zero-masking and merging behavior and introduces a method based on measuring whether cache-miss loads execute in parallel.

### Source excerpt

Some mostly too-low-level-to-care-about hardware details of the mask registers introduced in AVX-512.