# backside power delivery

Published articles for backside power delivery.

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## Beyond The Chip: How AI Is Reshaping Semiconductor Design And Manufacturing

DevFeed: [Beyond The Chip: How AI Is Reshaping Semiconductor Design And Manufacturing](<https://devfeed.tech/articles/beyond-the-chip-how-ai-is-reshaping-semiconductor-design-and-manufacturing-118091.md>)

Original publisher: [Read original article](<https://semiengineering.com/beyond-the-chip-how-ai-is-reshaping-semiconductor-design-and-manufacturing/>)

Author: Prashanth Aprameyan

Published: 2026-11-04T08:01:58Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [intel](<https://devfeed.tech/topics/intel.md>), [AI Trends](<https://devfeed.tech/topics/ai-trends.md>), [communications](<https://devfeed.tech/topics/communications.md>), [High-Performance Computing](<https://devfeed.tech/topics/high-performance-computing.md>)

Tags: [18a](<https://devfeed.tech/tags/18a.md>), [2-5d](<https://devfeed.tech/tags/2-5d.md>), [2-5d-integration](<https://devfeed.tech/tags/2-5d-integration.md>), [3d](<https://devfeed.tech/tags/3d.md>), [3d-integration](<https://devfeed.tech/tags/3d-integration.md>), [accelerators](<https://devfeed.tech/tags/accelerators.md>), [advanced](<https://devfeed.tech/tags/advanced.md>), [advanced-packaging](<https://devfeed.tech/tags/advanced-packaging.md>), [ai](<https://devfeed.tech/tags/ai.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [blogs-md](<https://devfeed.tech/tags/blogs-md.md>), [chip](<https://devfeed.tech/tags/chip.md>), [connectivity](<https://devfeed.tech/tags/connectivity.md>), [design](<https://devfeed.tech/tags/design.md>), [design-technology-co-optimization](<https://devfeed.tech/tags/design-technology-co-optimization.md>), [dtco](<https://devfeed.tech/tags/dtco.md>), [foundry-focus](<https://devfeed.tech/tags/foundry-focus.md>), [gaa-fets](<https://devfeed.tech/tags/gaa-fets.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [intel](<https://devfeed.tech/tags/intel.md>), [machine-learning](<https://devfeed.tech/tags/machine-learning.md>), [manufacturing](<https://devfeed.tech/tags/manufacturing.md>), [manufacturing-packaging-and-materials](<https://devfeed.tech/tags/manufacturing-packaging-and-materials.md>), [ml](<https://devfeed.tech/tags/ml.md>), [power-delivery](<https://devfeed.tech/tags/power-delivery.md>), [resilience](<https://devfeed.tech/tags/resilience.md>), [scaling](<https://devfeed.tech/tags/scaling.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [semiconductor-design](<https://devfeed.tech/tags/semiconductor-design.md>), [semiconductor-manufacturing](<https://devfeed.tech/tags/semiconductor-manufacturing.md>), [supply-chain](<https://devfeed.tech/tags/supply-chain.md>), [supply-chain-resilience](<https://devfeed.tech/tags/supply-chain-resilience.md>)

### AI overview

AI scaling is constrained by power delivery, connectivity, advanced packaging, and supply chain resilience as well as transistor scaling. The excerpt describes a shift from monolithic SoCs to modular chiplet systems, with UCIe for chiplet communication and packaging technologies such as EMIB-T and Foveros Direct. Intel 18A combines RibbonFET gate-all-around transistors with PowerVia backside power delivery; the source reports lower resistance and power noise, up to 10% higher cell utilization, and an 18% performance-per-watt improvement versus Intel 3, while noting added manufacturing complexity and a cost approach based on 32 nm frontside lower-metal pitches. Intel says AI and machine learning also support design tradeoff exploration, defect detection and diagnosis using factory image data, yield learning, and predictive equipment maintenance. Sovereign AI demand is linked to secure, geographically diverse manufacturing; Intel describes production capabilities across North America, Europe, and Asia.

### Source excerpt

Power delivery, connectivity, advanced packaging, and supply chain resilience are emerging as the primary constraints on AI scaling. The post Beyond The Chip: How AI Is Reshaping Semiconductor Design And Manufacturing appeared first on Semiconductor Engineering.

## Breaking The Memory Bottleneck In AI And HPC SoCs

DevFeed: [Breaking The Memory Bottleneck In AI And HPC SoCs](<https://devfeed.tech/articles/breaking-the-memory-bottleneck-in-ai-and-hpc-socs-90104.md>)

Original publisher: [Read original article](<https://semiengineering.com/breaking-the-memory-bottleneck-in-ai-and-hpc-socs/>)

Author: Synopsys

Published: 2026-10-19T07:03:19Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Feature Engineering](<https://devfeed.tech/topics/feature-engineering.md>), [Green Software](<https://devfeed.tech/topics/green-software.md>), [High-Performance Computing](<https://devfeed.tech/topics/high-performance-computing.md>)

Tags: [18a](<https://devfeed.tech/tags/18a.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [backside-power-delivery-network](<https://devfeed.tech/tags/backside-power-delivery-network.md>), [bspdn](<https://devfeed.tech/tags/bspdn.md>), [embedded](<https://devfeed.tech/tags/embedded.md>), [embedded-memory](<https://devfeed.tech/tags/embedded-memory.md>), [intel-18a](<https://devfeed.tech/tags/intel-18a.md>), [ip](<https://devfeed.tech/tags/ip.md>), [low-power-high-performance](<https://devfeed.tech/tags/low-power-high-performance.md>), [memory-ip](<https://devfeed.tech/tags/memory-ip.md>), [paper](<https://devfeed.tech/tags/paper.md>), [performance](<https://devfeed.tech/tags/performance.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [semiconductor-engineering](<https://devfeed.tech/tags/semiconductor-engineering.md>), [synopsys](<https://devfeed.tech/tags/synopsys.md>), [whitepapers](<https://devfeed.tech/tags/whitepapers.md>)

### AI overview

This white paper discusses embedded memory IP for AI and HPC SoCs as processes move to gate-all-around devices and backside power delivery. It describes Synopsys device-aware architectures, power-optimized designs, configurable compilers, and test-chip results on Intel 18A, including reported density improvements of 5-10% and power-performance gains of up to approximately 4%.

### Source excerpt

Opimizing embedded memory IP for RibbonFET and PowerVia. The post Breaking The Memory Bottleneck In AI And HPC SoCs appeared first on Semiconductor Engineering.

## Applied Materials Bets $5B on a New Model for Chip Innovation

DevFeed: [Applied Materials Bets $5B on a New Model for Chip Innovation](<https://devfeed.tech/articles/applied-materials-bets-5b-on-a-new-model-for-chip-innovation-85261.md>)

Original publisher: [Read original article](<https://www.eetimes.com/applied-materials-bets-5b-on-a-new-model-for-chip-innovation/>)

Author: Pat Brans

Published: 2026-10-12T16:59:01Z

Content type: article

Language: en

Sources: [EE Times](<https://devfeed.tech/sources/ee-times.md>)

Topics: [Materials science and engineering](<https://devfeed.tech/topics/materials-science-and-engineering.md>), [Chip design](<https://devfeed.tech/topics/chip-design.md>), [AI Research](<https://devfeed.tech/topics/ai-research.md>)

Tags: [advanced-packaging](<https://devfeed.tech/tags/advanced-packaging.md>), [ai-and-big-data](<https://devfeed.tech/tags/ai-and-big-data.md>), [ai-processors](<https://devfeed.tech/tags/ai-processors.md>), [analog](<https://devfeed.tech/tags/analog.md>), [analysis](<https://devfeed.tech/tags/analysis.md>), [applied-materials](<https://devfeed.tech/tags/applied-materials.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [bandwidth](<https://devfeed.tech/tags/bandwidth.md>), [broadcom](<https://devfeed.tech/tags/broadcom.md>), [business](<https://devfeed.tech/tags/business.md>), [chip-manufacturing](<https://devfeed.tech/tags/chip-manufacturing.md>), [chiplets](<https://devfeed.tech/tags/chiplets.md>), [community](<https://devfeed.tech/tags/community.md>), [designline](<https://devfeed.tech/tags/designline.md>), [digital](<https://devfeed.tech/tags/digital.md>), [education](<https://devfeed.tech/tags/education.md>), [ee-times](<https://devfeed.tech/tags/ee-times.md>), [ee-times-university](<https://devfeed.tech/tags/ee-times-university.md>), [eelife](<https://devfeed.tech/tags/eelife.md>), [eelive-electronic-design](<https://devfeed.tech/tags/eelive-electronic-design.md>), [eet](<https://devfeed.tech/tags/eet.md>), [electrical-engineering](<https://devfeed.tech/tags/electrical-engineering.md>), [electronic-components](<https://devfeed.tech/tags/electronic-components.md>), [electronic-engineering-times](<https://devfeed.tech/tags/electronic-engineering-times.md>), [electronics](<https://devfeed.tech/tags/electronics.md>), [embedded-systems](<https://devfeed.tech/tags/embedded-systems.md>), [fundamentals-courses](<https://devfeed.tech/tags/fundamentals-courses.md>), [learning](<https://devfeed.tech/tags/learning.md>), [mixed-signal](<https://devfeed.tech/tags/mixed-signal.md>), [news](<https://devfeed.tech/tags/news.md>), [opinion](<https://devfeed.tech/tags/opinion.md>), [part-search](<https://devfeed.tech/tags/part-search.md>), [product-search](<https://devfeed.tech/tags/product-search.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [semiconductors](<https://devfeed.tech/tags/semiconductors.md>), [soc](<https://devfeed.tech/tags/soc.md>), [software](<https://devfeed.tech/tags/software.md>), [tech-papers](<https://devfeed.tech/tags/tech-papers.md>), [technology](<https://devfeed.tech/tags/technology.md>), [video](<https://devfeed.tech/tags/video.md>)

### AI overview

Applied Materials opened its $5 billion EPIC Center to bring chipmakers, equipment suppliers, and researchers together on semiconductor technologies several generations ahead of production. The article describes how the center aims to shorten development and commercialization timelines through earlier collaboration across materials, processes, chip architectures, and manufacturing requirements. It also examines confidentiality controls, the company's commercial incentives, and the challenge of identifying technologies that cannot be manufactured economically.

### Source excerpt

Applied Materials' $5 billion EPIC Center brings chipmakers, equipment suppliers, and researchers together to accelerate semiconductor R&D and commercialization. The post Applied Materials Bets $5B on a New Model for Chip Innovation appeared first on EE Times.

## UCSC researchers explore backside clock meshes for 2 nm GAAFET technology

DevFeed: [UCSC researchers explore backside clock meshes for 2 nm GAAFET technology](<https://devfeed.tech/articles/backside-clock-meshes-cut-skew-and-power-in-2nm-nanosheets-ucsc-64920.md>)

Original publisher: [Read original article](<https://semiengineering.com/backside-clock-meshes-cut-skew-and-power-in-2nm-nanosheets-ucsc/>)

Author: Technical Paper Link

Published: 2026-10-05T18:07:21Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [ddr5](<https://devfeed.tech/topics/ddr5.md>), [LaTeX](<https://devfeed.tech/topics/latex.md>)

Tags: [2-nm](<https://devfeed.tech/tags/2-nm.md>), [backside-clock-meshes](<https://devfeed.tech/tags/backside-clock-meshes.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [backside-power-delivery-network](<https://devfeed.tech/tags/backside-power-delivery-network.md>), [bspdn](<https://devfeed.tech/tags/bspdn.md>), [buried-power-rails](<https://devfeed.tech/tags/buried-power-rails.md>), [chip](<https://devfeed.tech/tags/chip.md>), [clock-distribution](<https://devfeed.tech/tags/clock-distribution.md>), [clock-mesh](<https://devfeed.tech/tags/clock-mesh.md>), [design-space-exploration](<https://devfeed.tech/tags/design-space-exploration.md>), [design-verification](<https://devfeed.tech/tags/design-verification.md>), [gaafet](<https://devfeed.tech/tags/gaafet.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [gt2n](<https://devfeed.tech/tags/gt2n.md>), [hspice](<https://devfeed.tech/tags/hspice.md>), [nanosheet-transistors](<https://devfeed.tech/tags/nanosheet-transistors.md>), [nanosheets](<https://devfeed.tech/tags/nanosheets.md>), [openroad](<https://devfeed.tech/tags/openroad.md>), [paper](<https://devfeed.tech/tags/paper.md>), [performance](<https://devfeed.tech/tags/performance.md>), [physical-design](<https://devfeed.tech/tags/physical-design.md>), [power-delivery](<https://devfeed.tech/tags/power-delivery.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [routing](<https://devfeed.tech/tags/routing.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [through-silicon-vias](<https://devfeed.tech/tags/through-silicon-vias.md>), [transistors](<https://devfeed.tech/tags/transistors.md>), [tsv](<https://devfeed.tech/tags/tsv.md>), [uc-santa-cruz](<https://devfeed.tech/tags/uc-santa-cruz.md>), [university-of-california-santa-cruz](<https://devfeed.tech/tags/university-of-california-santa-cruz.md>)

### AI overview

University of California, Santa Cruz researchers report a design-space exploration of backside clock meshes for 2 nm GAAFET technology. Their paper examines using available backside metal layers for clock distribution, with connections to frontside flip-flops made through through-silicon vias.

### Source excerpt

Researchers at the University of California, Santa Cruz published a technical paper titled "Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology." Abstract Excerpt: "Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power... " read more The post Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC) appeared first on Semiconductor Engineering.

## Data Center Energy Trends Force A Rethink Of Chip Power Delivery

DevFeed: [Data Center Energy Trends Force A Rethink Of Chip Power Delivery](<https://devfeed.tech/articles/data-center-energy-trends-force-a-rethink-of-chip-power-delivery-62556.md>)

Original publisher: [Read original article](<https://semiengineering.com/data-center-energy-trends-force-a-rethink-of-chip-power-delivery/>)

Author: Kaladhar Radhakrishnam

Published: 2026-09-30T07:01:54Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Green Software](<https://devfeed.tech/topics/green-software.md>), [High-Performance Computing](<https://devfeed.tech/topics/high-performance-computing.md>), [nuclear energy for AI](<https://devfeed.tech/topics/nuclear-energy-for-ai.md>)

Tags: [2026](<https://devfeed.tech/tags/2026.md>), [ai](<https://devfeed.tech/tags/ai.md>), [ai-infrastructure](<https://devfeed.tech/tags/ai-infrastructure.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [blogs-md](<https://devfeed.tech/tags/blogs-md.md>), [chip](<https://devfeed.tech/tags/chip.md>), [data-center](<https://devfeed.tech/tags/data-center.md>), [data-centers](<https://devfeed.tech/tags/data-centers.md>), [foundry-focus](<https://devfeed.tech/tags/foundry-focus.md>), [intel](<https://devfeed.tech/tags/intel.md>), [intel-foundry](<https://devfeed.tech/tags/intel-foundry.md>), [manufacturing-packaging-and-materials](<https://devfeed.tech/tags/manufacturing-packaging-and-materials.md>), [performance](<https://devfeed.tech/tags/performance.md>), [power](<https://devfeed.tech/tags/power.md>), [power-consumption](<https://devfeed.tech/tags/power-consumption.md>), [power-delivery](<https://devfeed.tech/tags/power-delivery.md>)

### AI overview

The article describes rising power demand from AI, high-performance computing, and cloud services, and explains how data center power and cooling constraints affect system architecture. It discusses frontside power delivery tradeoffs and Intel Foundry's backside power delivery approach to improve routing and silicon efficiency.

### Source excerpt

Enabling silicon to operate closer to its true performance envelope without excessive guard banding. The post Data Center Energy Trends Force A Rethink Of Chip Power Delivery appeared first on Semiconductor Engineering.

## Driving Power Delivery Innovations For The AI Data Center

DevFeed: [Driving Power Delivery Innovations For The AI Data Center](<https://devfeed.tech/articles/driving-power-delivery-innovations-for-the-ai-data-center-52603.md>)

Original publisher: [Read original article](<https://semiengineering.com/driving-power-delivery-innovations-for-the-ai-data-center/>)

Author: Intel Foundry

Published: 2026-09-17T07:04:55Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [data centers](<https://devfeed.tech/topics/data-centers.md>), [Computing](<https://devfeed.tech/topics/computing.md>), [Scalability](<https://devfeed.tech/topics/scalability.md>), [High-Performance Computing](<https://devfeed.tech/topics/high-performance-computing.md>), [Artificial Intelligence](<https://devfeed.tech/topics/ai.md>), [systems](<https://devfeed.tech/topics/systems.md>), [intel](<https://devfeed.tech/topics/intel.md>)

Tags: [advanced](<https://devfeed.tech/tags/advanced.md>), [ai](<https://devfeed.tech/tags/ai.md>), [ai-data-centers](<https://devfeed.tech/tags/ai-data-centers.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [bpd](<https://devfeed.tech/tags/bpd.md>), [chip](<https://devfeed.tech/tags/chip.md>), [complexity](<https://devfeed.tech/tags/complexity.md>), [computing](<https://devfeed.tech/tags/computing.md>), [critical](<https://devfeed.tech/tags/critical.md>), [data-center](<https://devfeed.tech/tags/data-center.md>), [efficiency](<https://devfeed.tech/tags/efficiency.md>), [engineering](<https://devfeed.tech/tags/engineering.md>), [foundry](<https://devfeed.tech/tags/foundry.md>), [high-performance](<https://devfeed.tech/tags/high-performance.md>), [high-performance-computing](<https://devfeed.tech/tags/high-performance-computing.md>), [integrated-voltage-regulator](<https://devfeed.tech/tags/integrated-voltage-regulator.md>), [intel-foundry](<https://devfeed.tech/tags/intel-foundry.md>), [ivr](<https://devfeed.tech/tags/ivr.md>), [manufacturing-packaging-and-materials](<https://devfeed.tech/tags/manufacturing-packaging-and-materials.md>), [performance](<https://devfeed.tech/tags/performance.md>), [power](<https://devfeed.tech/tags/power.md>), [power-delivery](<https://devfeed.tech/tags/power-delivery.md>), [reliability](<https://devfeed.tech/tags/reliability.md>), [scale](<https://devfeed.tech/tags/scale.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [systems](<https://devfeed.tech/tags/systems.md>), [whitepapers](<https://devfeed.tech/tags/whitepapers.md>)

### AI overview

This paper examines power delivery challenges in AI and high-performance computing systems as rising current demands strain traditional power delivery networks. It discusses Intel Foundry innovations including backside power delivery, silicon capacitors, and integrated voltage regulators across accelerator, package, rack, and data center levels.

### Source excerpt

As AI systems scale, advanced power delivery innovations are becoming critical to performance, efficiency and reliability. The post Driving Power Delivery Innovations For The AI Data Center appeared first on Semiconductor Engineering.