# Cache Coherence

Published articles for Cache Coherence.

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## Local and distributed cache coherence: stale data caused by missed invalidation messages

DevFeed: [Local and distributed cache coherence: stale data caused by missed invalidation messages](<https://devfeed.tech/articles/local-cache-plus-distributed-cache-the-coherence-bill-nobody-budgets-for-39606.md>)

Original publisher: [Read original article](<https://ankit-rana.com/logs/54-local-and-distributed-cache-coherence/>)

Author: hello@ankit-rana.com

Published: 2026-09-17T00:00:00Z

Content type: opinion

Language: en

Sources: [Ankit Rana | Mechanical Sympathy](<https://devfeed.tech/sources/ankit-rana-mechanical-sympathy.md>)

Topics: [Caching](<https://devfeed.tech/topics/caching.md>), [Redis](<https://devfeed.tech/topics/redis.md>), [data](<https://devfeed.tech/topics/data.md>), [Network](<https://devfeed.tech/topics/network.md>)

Tags: [cache](<https://devfeed.tech/tags/cache.md>), [cache-coherence](<https://devfeed.tech/tags/cache-coherence.md>), [caching](<https://devfeed.tech/tags/caching.md>), [consistency](<https://devfeed.tech/tags/consistency.md>), [data](<https://devfeed.tech/tags/data.md>), [distributed-cache](<https://devfeed.tech/tags/distributed-cache.md>), [distributed-systems](<https://devfeed.tech/tags/distributed-systems.md>), [jvm](<https://devfeed.tech/tags/jvm.md>), [network](<https://devfeed.tech/tags/network.md>), [redis](<https://devfeed.tech/tags/redis.md>), [ttl](<https://devfeed.tech/tags/ttl.md>)

### AI overview

The article explains that adding an in-process cache in front of a distributed cache can improve latency but creates independently stale copies across service instances. It focuses on Redis pub/sub invalidation, which provides no persistence, acknowledgement, retry, or replay, allowing instances to miss invalidation messages and serve stale data until their TTL expires.

### Source excerpt

An in-process cache in front of a distributed cache removes a network hop and adds one independent copy of the data per instance, each of which can be stale on its own schedule. Invalidation is normally broadcast over pub/sub, which is fire and forget, so any instance that is restarting, garbage collecting or briefly disconnected simply misses the message and serves stale data until its TTL expires. That TTL is not a performance setting, it is the maximum duration of incorrectness.

## CPU Cache Flushing Fallacy

DevFeed: [CPU Cache Flushing Fallacy](<https://devfeed.tech/articles/cpu-cache-flushing-fallacy-13631.md>)

Original publisher: [Read original article](<https://mechanical-sympathy.blogspot.com/2013/02/cpu-cache-flushing-fallacy.html>)

Author: Martin Thompson (noreply@blogger.com)

Published: 2013-02-14T12:22:00Z

Content type: article

Language: en

Sources: [Mechanical Sympathy](<https://devfeed.tech/sources/mechanical-sympathy.md>)

Topics: [Cache](<https://devfeed.tech/topics/cache.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [x86](<https://devfeed.tech/topics/x86.md>), [Latency](<https://devfeed.tech/topics/latency.md>), [systems](<https://devfeed.tech/topics/systems.md>), [intel](<https://devfeed.tech/topics/intel.md>)

Tags: [cache-coherence](<https://devfeed.tech/tags/cache-coherence.md>), [core](<https://devfeed.tech/tags/core.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [cpu-cache](<https://devfeed.tech/tags/cpu-cache.md>), [intel](<https://devfeed.tech/tags/intel.md>), [ipc](<https://devfeed.tech/tags/ipc.md>), [latency](<https://devfeed.tech/tags/latency.md>), [memory-heirarchy](<https://devfeed.tech/tags/memory-heirarchy.md>), [performance](<https://devfeed.tech/tags/performance.md>), [systems](<https://devfeed.tech/tags/systems.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

The article explains why describing CPU-cache behavior as a cache "flush" can be misleading. It discusses cache hierarchies, interactions between caches and execution cores, memory latency, cache misses, and cache coherence, using Intel x86 server CPUs as a concrete example.

### Source excerpt

Even from highly experienced technologists I often hear talk about how certain operations cause a CPU cache to "flush". This seems to be illustrating a very common fallacy about how CPU caches work, and how the cache sub-system interacts with the execution cores. In this article I will attempt to explain the function CPU caches fulfil, and how the cores, which execute our programs of instructions, interact with them. For a concrete example I will dive into one of the latest Intel x86 server CPUs. Other CPUs use similar techniques to achieve the same ends. Most modern systems that execute our programs are shared-memory multi-processor systems in design. A shared-memory system has a single memory resource that is accessed by 2 or more independent CPU cores. Latency to main memory is highly variable from 10s to 100s of nanoseconds. Within 100ns it is possible for a 3.0GHz CPU to process up to 1200 instructions. Each Sandy Bridge core is capable of retiring up to 4 instructions-per-cycle (IPC) in parallel. CPUs employ cache sub-systems to hide this latency and allow them to exercise their huge capacity to process instructions. Some of these caches are small, very fast, and local to each core; others are slower, larger, and shared across cores. Together with registers and main-memory, these caches make up our non-persistent memory hierarchy. Next time you are developing an important algorithm, try pondering that a cache-miss is a lost opportunity to have executed ~500 CPU instructions! This is for a single-socket system, on a multi-socket system you can effectively double the lost opportunity as memory requests cross socket interconnects. Memory Hierarchy Figure 1. For the circa 2012 Sandy Bridge E class servers our memory hierarchy can be decomposed as follows: Registers: Within each core are separate register files containing 160 entries for integers and 144 floating point numbers. These registers are accessible within a single cycle and constitute the fastest memory a