# Chip design Published articles for Chip design. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Can you design a chip? Announcing the protocol emulator ASIC competition DevFeed: [Can you design a chip? Announcing the protocol emulator ASIC competition]() Original publisher: [Read original article]() Author: Benjamin Devlin Published: 2026-09-10T00:00:00Z Content type: release Language: en Sources: [Jane Street]() Topics: [Chip design](), [Protocol (disambiguation)](), [Hardware](), [Open Source](), [Emulator](), [cpu](), [Reverse Engineering](), [fpga](), [Formal methods](), [Verilog]() Tags: [chip-design](), [cpu](), [emulator](), [ethernet](), [firmware](), [formal-methods](), [fpga](), [hardware](), [i2c](), [jtag](), [open-source](), [peripheral](), [protocol](), [reverse-engineering]() ### AI overview Jane Street announces a competition to design an open-source, general-purpose protocol emulator ASIC. The proposed chip would use a small programmable CPU to read and write pins, count cycles, and implement protocols in firmware, with fabrication planned through IHP and Tiny Tapeout. ### Source excerpt Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here's our next challenge! This time, you're designing the chip, and we'll pay to fabricate our favorite designs! We're particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies! ## Qualcomm and Amazon Sign Multi-Generation Deal for Custom AI Inference Silicon and 1.6T Optical Interconnects DevFeed: [Qualcomm and Amazon Sign Multi-Generation Deal for Custom AI Inference Silicon and 1.6T Optical Interconnects]() Original publisher: [Read original article]() Author: Harold Fritts Published: 2026-09-08T17:17:46Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [Inference](), [Inference Performance](), [AI Infrastructure](), [Amazon Web Services](), [data centers](), [Chip design](), [networking](), [Amazon Bedrock](), [amazon]() Tags: [ai](), [ai-data-centers](), [ai-inference](), [ai-infrastructure](), [amazon-bedrock](), [aws](), [chip-design](), [cost](), [data-centers](), [dsp](), [efficiency](), [enterprise](), [networking](), [partnership](), [qualcomm]() ### AI overview Qualcomm Technologies and Amazon are collaborating across multiple generations to develop custom silicon for AWS AI data centers, primarily targeting AI inference. The agreement also covers 1.6T optical connectivity for data center networks and Qualcomm's use of AWS infrastructure, including Amazon Bedrock, for electronic design automation workloads. ### Source excerpt Qualcomm Technologies and Amazon have entered into a multi-generation collaboration to deliver customized silicon at scale for AWS's AI data centers, with AI inference as the primary target. The agreement pairs Qualcomm's power-efficient processing, silicon design, and system-level integration with Amazon's AI infrastructure, and is aimed at the compute, memory bandwidth, networking, and energy constraints The post Qualcomm and Amazon Sign Multi-Generation Deal for Custom AI Inference Silicon and 1.6T Optical Interconnects appeared first on StorageReview.com. ## MTIA 300: Meta's First Training Chip with Built-in NICs and Communication-Offloading Engines DevFeed: [MTIA 300: Meta's First Training Chip with Built-in NICs and Communication-Offloading Engines]() Original publisher: [Read original article]() Author: Rajiv Krishnamurthy; Wes Bland Published: 2026-08-24T17:45:52Z Content type: article Language: en Sources: [Engineering at Meta]() Topics: [recommendation systems](), [Language models]() Tags: [chip-design](), [communication](), [data-infrastructure](), [devinfra](), [gpu](), [hardware](), [inference](), [infrastructure](), [meta](), [networking-traffic](), [performance](), [production-engineering](), [training]() ### AI overview Meta describes MTIA 300, an in-house accelerator for training ranking and recommendation models, with built-in network chiplets and a co-designed HCCL communication library. The design targets communication-heavy distributed training by integrating RDMA NICs into the chip package and offloading communication work. ### Source excerpt MTIA 300 is the first of Meta's family of in-house training and inference accelerators optimized for training ranking and recommendation models. We're sharing how MTIA 300's built-in NIC chiplets allow it to meet the communication needs associated with training recommendation models with superior performance over general-purpose GPUs. By co-designing MTIA's communication library, HCCL, alongside the [...] Read More... The post MTIA 300: Meta's First Training Chip with Built-in NICs and Communication-Offloading Engines appeared first on Engineering at Meta. ## Google joins the OpenROAD Initiative as principal member to accelerate open source silicon innovation DevFeed: [Google joins the OpenROAD Initiative as principal member to accelerate open source silicon innovation]() Original publisher: [Read original article]() Author: Google Open Source (noreply@blogger.com) Published: 2026-08-11T18:30:00Z Content type: release Language: en Sources: [Google Open Source Blog]() Topics: [Google](), [Chip design](), [Open Source](), [toolchains](), [Continuous integration]() Tags: [chip-design](), [ci-cd](), [eda](), [google](), [open-source](), [openroad](), [semiconductors](), [toolchains](), [user-experience]() ### AI overview Google has joined the OpenROAD Initiative as a principal member and appointed Aaron Cunningham to its Governing Board. The partnership supports OpenROAD's open-source electronic design automation ecosystem through governance, ecosystem growth, workforce development, and technical improvements. ### Source excerpt by Ethan Mahintorabi & Aaron Cunningham, Hardware Toolchains Team Google is committed to advancing open source silicon innovation. We are excited to share that we have formally joined the OpenROAD Initiative (ORI), Inc. as a principal member. ORI is a nonprofit public benefit corporation dedicated to the open source electronic design automation (EDA) ecosystem. As part of this commitment, Aaron Cunningham has been appointed to the ORI Governing Board to represent Google and help drive the foundation's strategic direction, financial sustainability, and technical stewardship. Driving long-term open source sustainability The OpenROAD Initiative's mission is to advance and sustain the open source EDA ecosystem by fostering collaborative innovation across research, education, and industry--transforming ideas into silicon. Google's membership aligns directly with ORI's multi-year sustainability goals, supported by the US National Science Foundation's (NSF) Pathways to Enable Open-Source Ecosystems (POSE) program. With Google's participation and membership commitment, ORI will continue to strengthen, grow, and sustain its open source ecosystem through key vectors: Neutral Stewardship: Fostering transparent governance where no single company has outsized control over the code, ensuring the project remains inspectable, accessible, and community-driven. Ecosystem Growth: Supporting open and reproducible silicon research, developing robust design flows, and hosting global design contests. Workforce Development: Supporting global silicon skilling initiatives by expanding open source chip design curricula and collaborating with academic institutions and industrial training networks. Technical Strengthening: Enhancing continuous integration and deployment (CI/CD) pipelines, expanding PDK enablement, and improving user experience. Leadership perspectives "The OpenROAD Initiative is built on the vision of making chip design open and accessible to all--building a collaborative ecosyst ## Talking with Synopsys about the Physics of Chip Design at DAC 2026 DevFeed: [Talking with Synopsys about the Physics of Chip Design at DAC 2026]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-11T16:52:16Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Chip design](), [3D](), [Simulation and Design]() Tags: [3d](), [audio](), [automotive](), [battery](), [chip-design](), [communications](), [design](), [desktop](), [heat](), [interview](), [low-power](), [physics](), [techniques]() ### AI overview An edited audio interview with Synopsys executive Ravi Subramanian examines the physics involved in chip design and electronic design automation tools. The discussion covers larger chips, 2.5D and 3D multi-die integration, thermal management, low-power mobile systems, and automotive operating environments. ### Source excerpt Hello you fine Internet folks, ## AWS Trainium Frontier competition: Co-design models and kernels on purpose-built AI chips DevFeed: [AWS Trainium Frontier competition: Co-design models and kernels on purpose-built AI chips]() Original publisher: [Read original article]() Author: Louise Ping; John Gray; Emily Webber; Josh Longenecker Published: 2026-08-10T20:23:04Z Content type: article Language: en Sources: [Amazon Science homepage]() Topics: [AI Chat]() Tags: [aws-trainium](), [chip-design](), [hardware](), [kernels](), [language-models](), [machine-learning](), [model-architecture](), [neurips](), [performance](), [training]() ### AI overview AWS Trainium Frontier is a competition for training language models from scratch on Trainium while co-designing architectures, optimizers, training loops, and optional custom kernels under fixed compute and time budgets. ### Source excerpt A competition with a finalist ceremony during NeurIPS 2026, challenging researchers to train language models from scratch on Trainium, exploring what optimal architectures look like when the hardware changes. ## NVIDIA Nemotron 3 Ultra Leads Open Models on Accuracy and Efficiency in Agentic RTL Coding DevFeed: [NVIDIA Nemotron 3 Ultra Leads Open Models on Accuracy and Efficiency in Agentic RTL Coding]() Original publisher: [Read original article]() Author: Nirmal Kumar Juluru Published: 2026-07-27T00:45:00Z Content type: article Language: en Sources: [NVIDIA Developer](), [NVIDIA Technical Blog]() Topics: [coding](), [Verilog](), [AI-assisted coding](), [Nvidia](), [Artificial Intelligence](), [debugging](), [Benchmark](), [Code generation](), [Hardware](), [long-context]() Tags: [agentic](), [agentic-ai-generative-ai](), [ai](), [ai-agent](), [ai-agents](), [automation](), [benchmark](), [chip-design](), [code](), [code-generation](), [coding](), [debugging](), [developer-tools-techniques](), [efficiency](), [engineering](), [featured](), [hardware-semiconductor](), [llms](), [long-context](), [models](), [nemotron](), [nvidia](), [open](), [reasoning](), [top-stories](), [validation]() ### AI overview NVIDIA's article presents ACE-RTL and Nemotron 3 Ultra as a combined approach to agentic RTL coding. The workflow generates Verilog, runs simulations and other EDA checks, analyzes failures, and iteratively refines designs while maintaining debugging context. The CVDP benchmark evaluates accuracy and efficiency on realistic RTL generation, modification, debugging, and verification tasks. ### Source excerpt Modern chip design is increasingly limited by engineering time. Register transfer level (RTL) development and verification require specialized hardware... ## Graviton5's improved design increases speed and energy efficiency -- beyond Moore's law DevFeed: [Graviton5's improved design increases speed and energy efficiency -- beyond Moore's law]() Original publisher: [Read original article]() Author: Ali Saidi Published: 2026-06-10T15:00:00Z Content type: article Language: en Sources: [Amazon Science homepage]() Topics: [cpu](), [Amazon EC2]() Tags: [amazon-elastic-compute](), [architecture](), [cache](), [chip-design](), [cloud-and-systems](), [cpu](), [design](), [energy-efficiency](), [formal-verification](), [graviton](), [hardware](), [memory](), [performance](), [speed]() ### AI overview Amazon describes Graviton5 CPU and M9g/M9gd EC2 instances, highlighting more cores, faster memory and interconnects, improved branch prediction, and expanded cache capacity. ### Source excerpt A new chiplet architecture, custom die-to-die connectivity, and support for DDR5-8800 memory and the latest PCIe gen6 interconnects improve performance by 25% for general-purpose and agentic AI workloads.