# CPU Cache Published articles for CPU Cache. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Python sets and dictionaries can have quadratic-time performance DevFeed: [Python sets and dictionaries can have quadratic-time performance]() Original publisher: [Read original article]() Author: Daniel Lemire Published: 2026-09-03T14:01:45Z Content type: article Language: en Sources: [Daniel Lemire]() Topics: [Python](), [Data structures](), [hash](), [CPU Cache]() Tags: [array](), [cpu-cache](), [data-structure](), [hash](), [performance](), [python]() ### AI overview The article explains why Python sets and dictionaries are not formally constant-time in all cases. Hash collisions can make insertions and membership checks take quadratic time, while growing data structures can also incur reallocation and slower memory access as they exceed CPU cache capacity. ### Source excerpt In Python, the dict data structure is the conventional key-value structure. E.g., you might store a list of names as keys and have their phone numbers as values. Valentin Ignatev wrote this amusing post on X: It is indeed widely believed that, in the strict sense, the dict data structure and its companion, the set ... Continue reading Python sets and dictionaries can have quadratic-time performance ## 🍔🧠 How Cloudflare Freed 100TB RAM With 5 Cache Changes DevFeed: [🍔🧠 How Cloudflare Freed 100TB RAM With 5 Cache Changes]() Original publisher: [Read original article]() Author: Alexandre Zajac Published: 2026-08-31T15:30:54Z Content type: article Language: en Sources: [Hungry Minds]() Topics: [Cloudflare](), [Caching](), [Cache](), [CPU Cache](), [Software Engineering]() Tags: [cache](), [cloudflare](), [cpu-cache](), [software](), [software-engineering]() ### AI overview Cloudflare optimized the storage of DNS cache entries in its Big Pineapple platform through five changes, reducing per-entry memory usage by more than 50% and freeing roughly 100 terabytes across its fleet. The reported changes also increased insert throughput by 43% and reduced lookup latency by 19%. ### Source excerpt PLUS: Anthropic hardware standard 🤖, Rust state machines 🦀, Agent context compression 💾 ## Bloom Filters vs Counting Bloom Filters: When Deletions Kill Performance DevFeed: [Bloom Filters vs Counting Bloom Filters: When Deletions Kill Performance]() Original publisher: [Read original article]() Author: hello@ankit-rana.com Published: 2026-03-17T00:00:00Z Content type: article Language: en Sources: [Ankit Rana | Mechanical Sympathy]() Topics: [Algorithms](), [Caching](), [CPU Cache]() Tags: [bloom-filter](), [cache](), [cpu](), [cpu-cache](), [data-structures](), [distributed-systems](), [false-negative](), [false-positives](), [memory](), [performance](), [probabilistic](), [systems]() ### AI overview The article explains that standard Bloom filters support membership checks but not deletion because clearing shared bits can create false negatives. Counting Bloom filters enable deletion with counters, but their larger memory footprint can push lookups out of CPU cache and increase latency through random memory access. ### Source excerpt A standard Bloom filter is append-only because bits are shared between items, so clearing a bit for one item can create a false negative for another. Counting Bloom filters fix deletion by replacing each bit with a 4-bit or 8-bit counter, which multiplies the footprint four to eight times, pushes the structure out of L3, and turns each of the k lookups into a roughly 100 ns RAM hit instead of a 10 ns cache hit. ## Cuckoo Filters: Cache-Friendly Membership Checks With Deletions DevFeed: [Cuckoo Filters: Cache-Friendly Membership Checks With Deletions]() Original publisher: [Read original article]() Author: hello@ankit-rana.com Published: 2026-03-17T00:00:00Z Content type: tutorial Language: en Sources: [Ankit Rana | Mechanical Sympathy]() Topics: [CPU Cache](), [Caching](), [hash]() Tags: [cache](), [capacity](), [cpu-cache](), [cuckoo-filter](), [data-structures](), [false-positive](), [hash](), [insert](), [performance](), [probabilistic](), [spatial-locality](), [systems]() ### AI overview This article explains how Cuckoo filters support deletions while improving CPU cache behavior compared with counting Bloom filters. They check two specific buckets using compact fingerprints, but insertions can fail when kick-out chains exceed their limit, requiring capacity planning or overflow handling. ### Source excerpt A Cuckoo filter stores a one-to-two byte fingerprint in a hash table and finds it by checking exactly two buckets, the primary index and its XOR-derived alternate, instead of k random bit positions scattered across a large array. That spatial locality is the whole win on real CPUs. The trade-off is a hard edge: when the kick-out chain exceeds its limit, the insert fails outright. ## CPU Cache Flushing Fallacy DevFeed: [CPU Cache Flushing Fallacy]() Original publisher: [Read original article]() Author: Martin Thompson (noreply@blogger.com) Published: 2013-02-14T12:22:00Z Content type: article Language: en Sources: [Mechanical Sympathy]() Topics: [Cache](), [cpu](), [x86](), [Latency](), [systems](), [intel]() Tags: [cache-coherence](), [core](), [cpu](), [cpu-cache](), [intel](), [ipc](), [latency](), [memory-heirarchy](), [performance](), [systems](), [x86]() ### AI overview The article explains why describing CPU-cache behavior as a cache "flush" can be misleading. It discusses cache hierarchies, interactions between caches and execution cores, memory latency, cache misses, and cache coherence, using Intel x86 server CPUs as a concrete example. ### Source excerpt Even from highly experienced technologists I often hear talk about how certain operations cause a CPU cache to "flush". This seems to be illustrating a very common fallacy about how CPU caches work, and how the cache sub-system interacts with the execution cores. In this article I will attempt to explain the function CPU caches fulfil, and how the cores, which execute our programs of instructions, interact with them. For a concrete example I will dive into one of the latest Intel x86 server CPUs. Other CPUs use similar techniques to achieve the same ends. Most modern systems that execute our programs are shared-memory multi-processor systems in design. A shared-memory system has a single memory resource that is accessed by 2 or more independent CPU cores. Latency to main memory is highly variable from 10s to 100s of nanoseconds. Within 100ns it is possible for a 3.0GHz CPU to process up to 1200 instructions. Each Sandy Bridge core is capable of retiring up to 4 instructions-per-cycle (IPC) in parallel. CPUs employ cache sub-systems to hide this latency and allow them to exercise their huge capacity to process instructions. Some of these caches are small, very fast, and local to each core; others are slower, larger, and shared across cores. Together with registers and main-memory, these caches make up our non-persistent memory hierarchy. Next time you are developing an important algorithm, try pondering that a cache-miss is a lost opportunity to have executed ~500 CPU instructions! This is for a single-socket system, on a multi-socket system you can effectively double the lost opportunity as memory requests cross socket interconnects. Memory Hierarchy Figure 1. For the circa 2012 Sandy Bridge E class servers our memory hierarchy can be decomposed as follows: Registers: Within each core are separate register files containing 160 entries for integers and 144 floating point numbers. These registers are accessible within a single cycle and constitute the fastest memory a