# DDR chips

Published articles for DDR chips.

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## Xcena Cuts Data Movement to Address Memory Bottlenecks

DevFeed: [Xcena Cuts Data Movement to Address Memory Bottlenecks](<https://devfeed.tech/articles/xcena-cuts-data-movement-to-address-memory-bottlenecks-61013.md>)

Original publisher: [Read original article](<https://www.eetimes.com/xcena-cuts-data-movement-to-address-memory-bottlenecks/>)

Author: Gary Hilson

Published: 2026-09-28T07:30:00Z

Content type: news

Language: en

Sources: [EE Times](<https://devfeed.tech/sources/ee-times.md>)

Topics: [ddr5](<https://devfeed.tech/topics/ddr5.md>), [AI Infrastructure](<https://devfeed.tech/topics/ai-infrastructure.md>), [schema-evolution](<https://devfeed.tech/topics/schema-evolution.md>)

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### AI overview

Xcena says its MX1 CXL Type 3 device combines DDR5, SSD-backed capacity, and RISC-V cores to process data near memory. The company says it can reduce data movement for AI and database workloads, and describes software work on unified virtual memory, a modified LLVM-based compiler, and a CUDA-like SDK.

### Source excerpt

Xcena's MX1 uses CXL to push compute into memory by combining DDR5, SSDs, and RISC-V cores while easing programmability. The post Xcena Cuts Data Movement to Address Memory Bottlenecks appeared first on EE Times.