# Dram Published articles for Dram. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Hot Chips 2026: XCENA and Samsung's Near-Memory Compute CXL Device DevFeed: [Hot Chips 2026: XCENA and Samsung's Near-Memory Compute CXL Device]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-30T07:25:37Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [samsung](), [ddr5](), [RISC-V](), [data](), [Cache](), [Arm](), [intel]() Tags: [2026](), [arm](), [cache](), [capacity](), [clusters](), [compute](), [core](), [ddr5](), [dram](), [intel](), [memory](), [parallel](), [pcie](), [performance](), [risc-v](), [samsung]() ### AI overview The article examines XCENA and Samsung's MX1, a CXL memory expansion device that can host up to 2 TB of DDR5 memory, connect SSDs, and provide onboard compute through 3,072 RISC-V cores. It describes the device's memory bandwidth, cache hierarchy, power use, and focus on data-parallel workloads. ### Source excerpt CXL memory expansion, with a side of compute ## Hot Chips 2026: Samsung's Processing-in-Memory (PIM) DevFeed: [Hot Chips 2026: Samsung's Processing-in-Memory (PIM)]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-29T05:36:33Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [samsung](), [Latency]() Tags: [2026](), [compute](), [dram](), [latency](), [memory](), [model](), [operations](), [parallel](), [precision](), [samsung]() ### AI overview The article examines Samsung's LPDDR5X Processing-in-Memory implementation presented at Hot Chips 2026. It describes PIM blocks placed in each DRAM bank, enabling access to internal memory bandwidth and supporting MAC computations near the data. ### Source excerpt In-memory compute with LPDDR5X ## Hot Chips 2026: Applying High Bandwidth Flash (HBF) DevFeed: [Hot Chips 2026: Applying High Bandwidth Flash (HBF)]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-23T22:51:05Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Machine Learning & Artificial Intelligence](), [Inference](), [vllm](), [moe](), [Cache]() Tags: [2026](), [dram](), [machine-learning](), [memory](), [moe](), [ssd](), [vllm]() ### AI overview This article examines how High Bandwidth Flash (HBF) could support machine learning workloads. HBF does not yet have products; the discussion uses simulations and projections to explore software strategies, including moving Mixture-of-Experts components or KV cache data between HBF and faster memory, with vLLM as an example. ### Source excerpt Machine learning workloads have an insatiable appetite for DRAM capacity. Flash memory is cheaper per gigabyte of capacity than DRAM. Could it offer a way out? ## The Special Value Pi 4 was extremely short-lived DevFeed: [The Special Value Pi 4 was extremely short-lived]() Original publisher: [Read original article]() Author: jeff@jeffgeerling.com (Jeff Geerling) Published: 2026-07-08T14:00:00Z Content type: article Language: en Sources: [Jeff Geerling]() Topics: [Hardware](), [benchmarking](), [boot]() Tags: [benchmarking](), [blog](), [boot](), [dram](), [errors](), [hardware](), [kernel](), [memory](), [performance](), [pi-4](), [product](), [raspberry-pi](), [retail](), [shortage](), [speed](), [validation](), [video](), [youtube]() ### AI overview This article examines a short-lived "Special Value" Raspberry Pi 4 edition certified for 1.25 GHz instead of the usual 1.8 GHz. It compares the boards with retail Pi 4s, discusses their different DRAM packages, and reports boot, clock-speed, kernel-panic, and benchmarking observations. ### Source excerpt The 'Special Value' Pi 4 pictured above is probably the rarest Raspberry Pi I own--even rarer than my blue special edition Pi. A Raspberry Pi reseller briefly listed a special 'value edition' Pi 4. But the product page 404's now. While it was up, my curiosity got the better of me, and now I have two 'value' Pi 4s. What makes them a 'value'? They're only certified to run at 1.25 GHz (retail Pi 4s run at 1.8 GHz, and can usually be overclocked). ## Reclaim Ceph Capacity Through CephFS Transcoding DevFeed: [Reclaim Ceph Capacity Through CephFS Transcoding]() Original publisher: [Read original article]() Author: Anthony D'Atri Published: 2026-07-01T00:00:00Z Content type: article Language: en Sources: [Ceph Blog]() Topics: [Transcodings](), [Software](), [data]() Tags: [2026](), [4k](), [article](), [blog-post](), [ceph](), [cephfs](), [dram](), [efficiency](), [en-article](), [en-blog-post](), [enterprise](), [enterprise-storage](), [filesystem](), [fujitsu](), [git](), [hardware](), [performance](), [software](), [space](), [storage](), [tentacle]() ### AI overview This article addresses rising storage demands and hardware costs by discussing CephFS capacity efficiency. It describes replicated pools, Erasure Coding, and Fast EC in Ceph Tentacle, while the title identifies CephFS transcoding as the article's focus. ### Source excerpt Data expands to fill available storage (and beyond)! ¶ It used to be that enterprise storage meant 6RU rackmount Fujitsu 2351 Eagles, each holding a mind-boggling 380 MiB of data: enough for a whole company! Today that 380 MiB can't even hold a 4k pickleball video. Enterprises, educational instutitions, and really just about anyone these days demand storage capacities that start on the order of hundreds of tebibytes and rapidly grow to pebibytes. As this article is written in the spring of 2026, the memory market, which includes DRAM, SSDs, and legacy HDDs, has experienced a dramatic escalation of pricing. It is not uncommon to be quoted a price four times what the same hardware cost a year ago, and there are signs that it is going to get worse before it gets better. What's a poor ammonite to do?? Cephers find themselves between the Charybdis of quotes approaching Disaster Area's hypermathematics and the Scylla of hungry users armed with torches and git forks. Git forks, pitchforks. Get it? Sigh. Tough room. Anyway... Short of nuking the site from orbit, how do we make everyone happy, or at worst mildly discontented? Efficiency! CephFS ¶ CephFS is a popular, highly available and scalable software-defined POSIX-style distributed filesystem that can easily store tens of pebibytes of precious data. Or, alternately, cat videos. Ceph deployments often begin small, with replicated pools for perceived performance needs. As the cluster grows to more nodes and more data, it may become feasible and desirable to switch to Erasure Coding (EC) to make more efficient use of raw capacity. An EC pool thus can require substantially less raw storage for a given amount of user data, or store gobs more user data on a given amount of raw capacity This EC overhead table presents efficiency (space amplification) factors for a spectrum of EC profiles. Replicated pools usually maintain three copies of data, so for comparison they manifest an overhead factor of 3.0. EC 4+2 or 6+3 presents a ## The RUM Conjecture: You Cannot Optimize Reads, Updates, and Memory at Once DevFeed: [The RUM Conjecture: You Cannot Optimize Reads, Updates, and Memory at Once]() Original publisher: [Read original article]() Author: hello@ankit-rana.com Published: 2026-03-17T00:00:00Z Content type: article Language: en Sources: [Ankit Rana | Mechanical Sympathy]() Topics: [systems](), [Databases](), [Apache Cassandra](), [rocksdb](), [MySQL](), [PostgreSQL]() Tags: [b-tree](), [capacity](), [cassandra](), [database](), [databases](), [dram](), [indexing](), [latency](), [memory](), [mysql](), [node](), [performance](), [rocksdb](), [storage-engine](), [system-design]() ### AI overview The article explains the RUM Conjecture, which describes a tradeoff among read overhead, update overhead, and memory overhead in database indexes and storage engines. It compares B-Trees, LSM-Trees, and hash indexes to show how each optimizes different tradeoffs. ### Source excerpt You can strictly optimise at most two of read overhead, update overhead, and memory overhead; the third will be expensive. B-Trees optimise reads and memory and pay on writes. LSM-Trees optimise writes and memory and pay on reads. Hash indexes optimise reads and writes and pay in RAM. The useful question is not whether a database is good but which corner it optimises and what you are willing to pay for the other two. ## Supporting Rowhammer research to protect the DRAM ecosystem DevFeed: [Supporting Rowhammer research to protect the DRAM ecosystem]() Original publisher: [Read original article]() Author: Kimberly Samra (noreply@blogger.com) Published: 2025-09-15T17:01:00Z Content type: article Language: en Sources: [Google Online Security]() Topics: [Hardware](), [Vulnerabilities](), [ddr5](), [Google](), [Security]() Tags: [ddr5](), [dram](), [google](), [hardware](), [none](), [research](), [rowhammer](), [security](), [vulnerabilities]() ### AI overview Google describes Rowhammer as a DRAM hardware vulnerability in which repeated access to memory rows can cause bit flips in adjacent rows. The article explains the security risks, discusses mitigations such as ECC and Target Row Refresh for DDR5, and outlines Google-supported research and test platforms intended to improve defenses. ### Source excerpt Posted by Daniel Moghimi Rowhammer is a complex class of vulnerabilities across the industry. It is a hardware vulnerability in DRAM where repeatedly accessing a row of memory can cause bit flips in adjacent rows, leading to data corruption. This can be exploited by attackers to gain unauthorized access to data, escalate privileges, or cause denial of service. Hardware vendors have deployed various mitigations, such as ECC and Target Row Refresh (TRR) for DDR5 memory, to mitigate Rowhammer and enhance DRAM reliability. However, the resilience of those mitigations against sophisticated attackers remains an open question. To address this gap and help the ecosystem with deploying robust defenses, Google has supported academic research and developed test platforms to analyze DDR5 memory. Our effort has led to the discovery of new attacks and a deeper understanding of Rowhammer on the current DRAM modules, helping to forge the way for further, stronger mitigations. What is Rowhammer? Rowhammer exploits a vulnerability in DRAM. DRAM cells store data as electrical charges, but these electric charges leak over time, causing data corruption. To prevent data loss, the memory controller periodically refreshes the cells. However, if a cell discharges before the refresh cycle, its stored bit may corrupt. Initially considered a reliability issue, it has been leveraged by security researchers to demonstrate privilege escalation attacks. By repeatedly accessing a memory row, an attacker can cause bit flips in neighboring rows. An adversary can exploit Rowhammer via: Reliably cause bit flips by repeatedly accessing adjacent DRAM rows. Coerce other applications or the OS into using these vulnerable memory pages. Target security-sensitive code or data to achieve privilege escalation. Or simply corrupt system's memory to cause denial of service. Previous work has repeatedly demonstrated the possibility of such attacks from software [Revisiting rowhammer, Are we susceptible to rowhammer ## Thread Count Scaling Part 4. CloverLeaf and CPython DevFeed: [Thread Count Scaling Part 4. CloverLeaf and CPython]() Original publisher: [Read original article]() Author: Denis Bakhvalov Published: 2024-05-10T04:00:00Z Content type: article Language: en Sources: [Denis Bakhvalov]() Topics: [benchmarking](), [Concurrency]() Tags: [book-chapters](), [case-study](), [dram](), [hpc](), [memory](), [metric](), [performance](), [performance-analysis](), [scale](), [speed](), [thread]() ### AI overview The article examines CloverLeaf and CPython thread-count scaling. It reports that CloverLeaf performance stops increasing after three threads because memory bandwidth becomes the limiting factor. Replacing two memory modules with faster DDR4 modules improves performance by 10% to 33% as thread count increases. ### Source excerpt Subscribe to my newsletter, support me on Patreon, Github, or by PayPal donation. This blog is an excerpt from the book. More details in the introduction. CloverLeaf is a hydrodynamics workload. We will not dig deep into the details of the underlying algorithm as it is not relevant to this case study. CloverLeaf uses OpenMP to parallelize the workload. Similar to other HPC workloads, we should expect CloverLeaf to scale well. ## Persistent memory - Introduction DevFeed: [Persistent memory - Introduction]() Original publisher: [Read original article]() Published: 2022-04-28T00:00:00Z Content type: tutorial Language: en Sources: [Kt. Academy]() Topics: [Persistence](), [Data structures](), [data](), [NVMe]() Tags: [data-structure](), [dram](), [motherboard](), [nvme](), [persistence](), [storage](), [workshop-learning-programming]() ### AI overview An introduction to persistent memory, covering its characteristics, memory mapping, addressability, and differences from block storage. It also explains full and selective persistence through the example of building a persistent dictionary. ### Source excerpt Do you want to learn about persistent memory? Join this journey to explore persistent memory and build a persistent dictionary. ## Can cached memory accesses do double-sided row hammering? DevFeed: [Can cached memory accesses do double-sided row hammering?]() Original publisher: [Read original article]() Author: Mark Seaborn (noreply@blogger.com) Published: 2015-05-11T22:35:00Z Content type: opinion Language: en Sources: [Mark Seaborn]() Topics: [Cache](), [cpu]() Tags: [cache](), [cpu](), [dram](), [mapping](), [rowhammer](), [xor]() ### AI overview This article examines whether double-sided Rowhammer attacks can be performed using cached memory accesses instead of CLFLUSH. For the author's Sandy Bridge test machine, cache-set, DRAM-bank, and row-address constraints make selecting suitable addresses impossible, leaving single-sided hammering or two sets of 13 addresses as possible approaches. ### Source excerpt There are indications that it is possible to cause bit flips in memory by row hammering without using CLFLUSH, using normal cached memory accesses. This makes me wonder: Is it possible to do double-sided row hammering using cached memory accesses, or only single-sided row hammering? The former is more likely to cause bit flips, and might be the only way to cause bit flips on some machines, such as those using a 2x refresh rate -- i.e. those configured to refresh DRAM every 32ms instead of every 64ms. (See the rowhammer blog post for more background.) The answer appears to be "no" -- at least on my test machine. For this machine (which has a Sandy Bridge CPU), I figured out how physical addresses map to cache sets and to banks and rows in DRAM. We can use these mappings to answer questions about what kinds of row hammering are possible using cached memory accesses. More specifically, my question is this: For a machine with an N-way L3 cache, is it possible to pick N+1 addresses that map to the same cache set, where at least two of these addresses map to rows R-1 and R+1 in one bank (for some neighbouring row R)? If so, repeatedly accessing these addresses would cause cache misses that cause rows R-1 and R+1 to be repeatedly activated. That puts more stress on row R (the victim row) than repeatedly activating only row R-1 or row R+1. The answer to this is "no": It's not possible to pick two such physical addresses. Here's why: Suppose we have two such addresses, A and B. Then: The addresses map to the same bank, so: (1): A[14:17] ^ A[18:21] = B[14:17] ^ B[18:21] (using the bank/row XOR scheme I described previously) The addresses are 2 rows apart, so: (2): A[18:32] + 2 = B[18:32] The addresses map to the same cache set, so: (3): A[6:17] = B[6:17] (also, SliceHash(A[17:32]) = SliceHash(B[17:32]), but we don't need this property) (2) implies that A[19] = ~B[19]. (3) implies that A[14:17] = B[14:17]. Combining that with (1) gives A[18:21] = B[18:21]. That implies A[19] = ## How physical addresses map to rows and banks in DRAM DevFeed: [How physical addresses map to rows and banks in DRAM]() Original publisher: [Read original article]() Author: Mark Seaborn (noreply@blogger.com) Published: 2015-05-04T22:57:00Z Content type: article Language: en Sources: [Mark Seaborn]() Topics: [cpu](), [intel](), [bug](), [Testing]() Tags: [cpu](), [dram](), [intel](), [memory](), [rowhammer](), [testing]() ### AI overview The article examines how Intel Sandy Bridge memory controllers map physical addresses to DRAM rows, banks, and columns. Using a vulnerable test machine, it relates the mapping to Rowhammer testing and describes inferring and checking the mapping from observed aggressor and victim addresses. ### Source excerpt In my previous blog post, I discussed how Intel Sandy Bridge CPUs map physical addresses to locations in the L3 cache. Now I'll discuss how these CPUs' memory controllers map physical addresses to locations in DRAM -- specifically, to row, bank and column numbers in DRAM modules. Let's call this the DRAM address mapping. I'll use one test machine as a case study. Motivation: the rowhammer bug I am interested in the DRAM address mapping because it is relevant to the "rowhammer" bug. Rowhammer is a problem with some DRAM modules whereby certain pessimal memory access patterns can cause memory corruption. In these DRAMs, repeatedly activating a row of memory (termed "row hammering") can produce electrical disturbances that produce bit flips in vulnerable cells in adjacent rows of memory. These repeated row activations can be caused by repeatedly accessing a pair of DRAM locations that are in different rows of the same bank of DRAM. Knowing the DRAM address mapping is useful because it tells us which pairs of addresses satisfy this "same bank, different row" (SBDR) property. Guessing and checking an address mapping For my case study, I have a test machine containing DRAM that is vulnerable to the rowhammer problem. Running rowhammer_test on this machine demonstrates bit flips. I'd like to know what the DRAM address mapping is for this machine, but apparently it isn't publicly documented: This machine has a Sandy Bridge CPU, but Intel don't document the address mapping used by these CPUs' memory controllers. rowhammer_test does not actually need to identify SBDR address pairs. rowhammer_test just repeatedly tries hammering randomly chosen address pairs. Typically 1/8 or 1/16 of these pairs will be SBDR pairs, because our machine has 8 banks per DIMM (and 16 banks in total). So, while we don't need to know the DRAM address mapping to cause bit flips on this machine, knowing it would help us be more targeted in our testing. Though the address mapping isn't documented, I fo ## The DRAM rowhammer bug is exploitable DevFeed: [The DRAM rowhammer bug is exploitable]() Original publisher: [Read original article]() Author: Mark Seaborn (noreply@blogger.com) Published: 2015-03-10T21:53:00Z Content type: article Language: en Sources: [Mark Seaborn]() Topics: [bug](), [Security](), [Kernel]() Tags: [blog](), [bug](), [dram](), [kernel](), [project](), [rowhammer](), [security]() ### AI overview The article discusses the security implications of the DRAM rowhammer bug and notes published findings on exploiting it to gain kernel privileges. ### Source excerpt I've been researching the DRAM rowhammer issue and its security implications for a while. We've finally published our findings on the Project Zero blog: Exploiting the DRAM rowhammer bug to gain kernel privileges.