# Fab Technology Co-Optimization

Published articles for Fab Technology Co-Optimization.

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## Accelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins

DevFeed: [Accelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins](<https://devfeed.tech/articles/accelerating-manufacturing-aware-simulations-for-photonic-integrated-circuits-with-ftco-and-digital-twins-91872.md>)

Original publisher: [Read original article](<https://semiengineering.com/accelerating-manufacturing-aware-simulations-for-photonic-integrated-circuits-with-ftco-and-digital-twins/>)

Author: Silvaco

Published: 2026-10-21T07:01:23Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Simulation](<https://devfeed.tech/topics/simulation.md>), [Chip design](<https://devfeed.tech/topics/chip-design.md>)

Tags: [3d](<https://devfeed.tech/tags/3d.md>), [ai](<https://devfeed.tech/tags/ai.md>), [design](<https://devfeed.tech/tags/design.md>), [digital-twin](<https://devfeed.tech/tags/digital-twin.md>), [digital-twins](<https://devfeed.tech/tags/digital-twins.md>), [digital-twins-for-pics](<https://devfeed.tech/tags/digital-twins-for-pics.md>), [doe](<https://devfeed.tech/tags/doe.md>), [experiments](<https://devfeed.tech/tags/experiments.md>), [fab-technology-co-optimization](<https://devfeed.tech/tags/fab-technology-co-optimization.md>), [ftco](<https://devfeed.tech/tags/ftco.md>), [gds-layout](<https://devfeed.tech/tags/gds-layout.md>), [gpu](<https://devfeed.tech/tags/gpu.md>), [gpu-accelerated](<https://devfeed.tech/tags/gpu-accelerated.md>), [import](<https://devfeed.tech/tags/import.md>), [manufacturing](<https://devfeed.tech/tags/manufacturing.md>), [manufacturing-packaging-and-materials](<https://devfeed.tech/tags/manufacturing-packaging-and-materials.md>), [modeling](<https://devfeed.tech/tags/modeling.md>), [photonic-integrated-circuit](<https://devfeed.tech/tags/photonic-integrated-circuit.md>), [photonic-integrated-circuits](<https://devfeed.tech/tags/photonic-integrated-circuits.md>), [pics](<https://devfeed.tech/tags/pics.md>), [pics-simulation](<https://devfeed.tech/tags/pics-simulation.md>), [process](<https://devfeed.tech/tags/process.md>), [silvaco](<https://devfeed.tech/tags/silvaco.md>), [simulation](<https://devfeed.tech/tags/simulation.md>), [simulations](<https://devfeed.tech/tags/simulations.md>), [surrogate-modeling](<https://devfeed.tech/tags/surrogate-modeling.md>), [whitepapers](<https://devfeed.tech/tags/whitepapers.md>), [workflow](<https://devfeed.tech/tags/workflow.md>)

### AI overview

The excerpt describes an FTCO workflow that models fabrication variation to improve photonic integrated circuit (PIC) performance predictions beyond idealized, as-drawn FDTD. It connects GDS layout import, 3D process simulation, GPU-accelerated FDTD, design of experiments, and AI-based surrogate modeling. The authors report that including manufacturing variation produces results aligned with experimentally reported results. Their directional-coupler DOE spans 25 combinations of four process variations; each 65-million-cell 3D FDTD model completes in under 10 hours on a single NVIDIA A100 workstation. The resulting digital twin is described as giving non-simulation experts real-time access to process-to-performance relationships.

### Source excerpt

Fab workflow connects GDS layout import, 3D process simulation, GPU-accelerated FDTD, design of experiments, with AI-based surrogate modeling. The post Accelerating Manufacturing-Aware Simulations For Photonic Integrated Circuits With FTCO And Digital Twins appeared first on Semiconductor Engineering.