# fpga Published articles for fpga. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Can you design a chip? Announcing the protocol emulator ASIC competition DevFeed: [Can you design a chip? Announcing the protocol emulator ASIC competition]() Original publisher: [Read original article]() Author: Benjamin Devlin Published: 2026-09-10T00:00:00Z Content type: release Language: en Sources: [Jane Street]() Topics: [Chip design](), [Protocol (disambiguation)](), [Hardware](), [Open Source](), [Emulator](), [cpu](), [Reverse Engineering](), [fpga](), [Formal methods](), [Verilog]() Tags: [chip-design](), [cpu](), [emulator](), [ethernet](), [firmware](), [formal-methods](), [fpga](), [hardware](), [i2c](), [jtag](), [open-source](), [peripheral](), [protocol](), [reverse-engineering]() ### AI overview Jane Street announces a competition to design an open-source, general-purpose protocol emulator ASIC. The proposed chip would use a small programmable CPU to read and write pins, count cycles, and implement protocols in firmware, with fabrication planned through IHP and Tiny Tapeout. ### Source excerpt Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here's our next challenge! This time, you're designing the chip, and we'll pay to fabricate our favorite designs! We're particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies! ## FREE-WILi 2 portable hacking multitool features two RP2350 MCUs, ESP32-C5, ICE40 FPGA, and Raspberry Pi CM0 DevFeed: [FREE-WILi 2 portable hacking multitool features two RP2350 MCUs, ESP32-C5, ICE40 FPGA, and Raspberry Pi CM0]() Original publisher: [Read original article]() Author: Debashis Das Published: 2026-09-09T00:00:02Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Embedded Systems](), [Raspberry Pi](), [ESP32-C5](), [Hardware](), [Hacking](), [Linux]() Tags: [802-15-4](), [ble](), [bluetooth](), [broadcom-bcmxxxx](), [c-c-plus-plus](), [can](), [electronics](), [embedded](), [esp32](), [esp32-c5](), [espressif](), [fpga](), [hack](), [hacking](), [hardware](), [lattice](), [linux](), [lora](), [meshtastic](), [nfc](), [open-hardware](), [python](), [raspberry-pi](), [raspberry-pi-rp2350](), [rfid](), [rust](), [security](), [som](), [stm32](), [stmicro-stm32](), [texas-instruments-simplelink](), [thread](), [tools](), [video](), [wi-fi](), [wifi-6](), [wireless](), [zigbee]() ### AI overview The FREE-WILi 2 Founder Edition is an open-hardware, portable multitool for hardware hackers, pentesters, and embedded-system developers. It combines two Raspberry Pi RP2350 MCUs, an ESP32-C5, a Lattice ICE40UP5K FPGA, and a Raspberry Pi CM0 capable of running a full Linux OS, along with touchscreen controls, expansion headers, and multiple wireless interfaces. ### Source excerpt The FREE-WILi 2 (Founder Edition) is an open-hardware, portable hacking multitool and lab designed for hardware hackers, pentesters, and embedded system developers. Designed as an "open electronics multitool," it combines a range of chips and modules into a handheld device, including two Raspberry Pi RP2350 MCUs, an ESP32-C5 for wireless connectivity, a Lattice ICE40UP5K FPGA, and a Raspberry Pi CM0 for running a full Linux OS. The device also features a 3.5-inch capacitive touchscreen, a 14-button physical interface, and modular "Orca" headers for hardware expansion. Its wireless features include 2.4/5GHz Wi-Fi, Bluetooth, LoRa, sub-GHz RF, NFC, 125kHz RFID, and IR. These features make it very suitable for wireless testing, embedded hardware debugging, real-time control, electronics development, and retro gaming, with support for Adafruit Fruit Jam, PICO-8, and Doom. FREE-WILi 2 specifications: Compute Main MCUs - 2x Raspberry Pi RP2350B (One for main controls, one dedicated to display) SoM - Raspberry [...] The post FREE-WILi 2 portable hacking multitool features two RP2350 MCUs, ESP32-C5, ICE40 FPGA, and Raspberry Pi CM0 appeared first on CNX Software - Embedded Systems News. ## Circuit Valley CHC5 - A modular USB, HDMI, and Ethernet camera system (Crowdfunding) DevFeed: [Circuit Valley CHC5 - A modular USB, HDMI, and Ethernet camera system (Crowdfunding)]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-02T07:25:10Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [webcam](), [Hardware](), [USB](), [hdmi](), [Ethernet](), [SOC](), [Embedded Systems](), [Linux](), [SDK](), [Open Source]() Tags: [arm](), [buildroot](), [c-c-plus-plus](), [camera](), [computer-vision](), [edge-ai](), [embedded-systems](), [ethernet](), [fpga](), [hardware](), [hdmi](), [kickstarter](), [linux](), [open-source](), [poe](), [sdk](), [soc](), [usb](), [video](), [xilinx-zynq]() ### AI overview CNX Software reports on Circuit Valley's CHC5, a modular camera system built around an AMD/Xilinx Zynq-7020 SoC FPGA. It supports interchangeable sensor and lens configurations, USB, HDMI, and Gigabit Ethernet interfaces, and image-processing and machine-vision workloads. ### Source excerpt Circuit Valley's CHC5 is a modular camera system based on a Core board powered by an AMD/Xilinx Zynq-7020 SoC FPGA, a range of interface boards with USB, HDMI, or Ethernet (PoE), various sensor boards, and a metal enclosure. The solution can be customized with different lens objectives and different sensors with MIPI D-PHY, LVDS, Sub-LVDS, Low Voltage LVDS, or SLVS interfaces. The Zynq-7020's Cortex-A9 cores can handle complex tasks, while the FPGA fabric takes care of high-speed calculation and correction on the image, and can also be leveraged for AI/machine-vision-specific algorithms or complex low-latency hardware acceleration. CHC5 specifications: Core board SoC - Xilinx AMD Zynq-7020 SoC FPGA CPU - Dual-core Arm Cortex-A9 processor FPGA - 85K logic cells, 4.9Mb Block RAM, 220 DSP slices System Memory - 1GB DDR3 Storage 1 Gbit flash memory MicroSD card slot ISP - Full-fledged ISP implemented on FPGA fabric Multiple interface boards with 10Gbps [...] The post Circuit Valley CHC5 - A modular USB, HDMI, and Ethernet camera system (Crowdfunding) appeared first on CNX Software - Embedded Systems News. ## Results from the Advent of FPGA Challenge DevFeed: [Results from the Advent of FPGA Challenge]() Original publisher: [Read original article]() Author: Anish Singhani Published: 2026-02-11T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [fpga](), [Advent of Code](), [Hardware](), [Verilog](), [Algorithms]() Tags: [advent-of-code](), [algorithms](), [competition](), [fpga](), [hardware](), [writeup]() ### AI overview Jane Street reports the results of its Advent of FPGA Challenge, a hardware-design competition run alongside Advent of Code. The article describes participation statistics, the hardware description languages used, and examples of notable submissions. ### Source excerpt At the end of last year, we decided to try something new: a challenge that would run alongside Advent of Code, where we asked the community to show us how they could design hardware to solve the same problems. We had no idea what level of participation to expect, but we received a huge number of submissions, many of which were incredibly creative! ## Advent of FPGA -- A Jane Street Challenge DevFeed: [Advent of FPGA -- A Jane Street Challenge]() Original publisher: [Read original article]() Author: Anish Singhani Published: 2025-11-24T00:00:00Z Content type: release Language: en Sources: [Jane Street]() Topics: [Advent of Code](), [fpga](), [Programming](), [Open Source]() Tags: [2025](), [advent-of-code](), [blog](), [blog-post](), [code](), [fpga](), [open-source]() ### AI overview Jane Street announces the 2025 Advent of FPGA Challenge, inviting participants to implement Advent of Code puzzles as synthesizable RTL with realistic I/O. Submissions must include open-source code, a testbench, and documentation, with Hardcaml encouraged but other RTL languages accepted. ### Source excerpt Update: We got over 200 submissions to this challenge, spanning a wide variety of HDL languages and hardware platforms! We featured our favorite submissions in the results blog post, check it out here ## Advent of Hardcaml DevFeed: [Advent of Hardcaml]() Original publisher: [Read original article]() Author: Anish Singhani Published: 2025-03-22T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [Advent of Code](), [fpga](), [Reason](), [Programming](), [Algorithms](), [Simulation](), [Open Source]() Tags: [advent-of-code](), [algorithms](), [fpga](), [ocaml](), [open-source](), [programming](), [simulation](), [software]() ### AI overview A Jane Street developer describes implementing Advent of Code 2024 puzzles on an FPGA using Hardcaml, an open-source hardware description language embedded in OCaml. The article discusses adapting algorithms to FPGA constraints and using Hardcaml for simulation, RTL compilation, hardware design, and synthesis. ### Source excerpt Update: For the 2025 Advent of Code, we ran an Advent of FPGA Challenge where we invited the community to implement their own synthesizable solutions to this year's puzzles! We got over 200 submissions spanning a wide variety of HDL languages and hardware platforms, check out our favorite solutions in the results blog post ## HEIR advances integration of fully homomorphic encryption with accelerator hardware DevFeed: [HEIR advances integration of fully homomorphic encryption with accelerator hardware]() Original publisher: [Read original article]() Published: 2024-11-15T18:25:51Z Content type: opinion Language: en Sources: [Jeremy Kun]() Topics: [FHE](), [homomorphic encryption](), [Compiler](), [Hardware](), [fpga](), [GPU](), [Inference]() Tags: [compiler](), [encryption](), [fhe](), [fpga](), [gpu](), [hardware](), [inference](), [shortform]() ### AI overview This developer update describes progress on HEIR, a compiler toolchain for fully homomorphic encryption. The project is working with hardware vendors and researchers to target GPU, FPGA, ASIC, optical, and TPU accelerators, while contributing to standardized hardware interfaces and optimizing FHE compilation and machine learning inference. ### Source excerpt In my little corner of the FHE world, things have been steadily heating up. For those who don't know, my main work project right now is HEIR (Homomorphic Encryption Intermediate Representation), a compiler toolchain for fully homomorphic encryption (FHE). For an extended introduction see this talk from October 2023. The primary focus of HEIR is to compile to FHE hardware accelerators. And boy there are a lot of them. There are GPU and FPGA accelerators, as well as special purpose ASICs and even optical accelerators (discrete Fourier transforms at the speed of light). ## Accelerating zk-SNARKs - MSM and NTT algorithms on FPGAs with Hardcaml DevFeed: [Accelerating zk-SNARKs - MSM and NTT algorithms on FPGAs with Hardcaml]() Original publisher: [Read original article]() Author: Andrew Ray Published: 2022-12-07T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [Zero-knowledge proof](), [Cryptography](), [fpga](), [Algorithms, Complexity](), [Open Source]() Tags: [algorithms](), [blockchain](), [cryptography](), [fpga](), [open-source](), [web3](), [zero-knowledge]() ### AI overview This article describes Jane Street's ZPrize submissions for accelerating zk-SNARK proof construction with FPGA designs built using the open-source Hardcaml libraries. Its MSM solution on the BLS12-377 curve won first place in the MSM track, while its NTT solution took second place in the NTT track. ### Source excerpt In 2022 a consortium of companies ran an international competition, called the ZPrize, to advance the state of the art in "zero-knowledge" cryptography. We decided to have a go in our free time at submitting solutions to both the Multi-Scalar Multiplication (MSM) and Number Theoretic Transform (NTT) tracks, using the same open source Hardcaml libraries that Jane Street uses for our own FPGA development. We believe by using Hardcaml we were able to more efficiently and robustly come up with designs in the short competition period. These designs also interact with the standard vendor RTL flow and so we hope they will be useful to others. ## Growing the Hardcaml toolset DevFeed: [Growing the Hardcaml toolset]() Original publisher: [Read original article]() Author: Andrew Ray Published: 2020-12-01T00:00:00Z Content type: release Language: en Sources: [Jane Street]() Topics: [Library](), [Documentation](), [fpga](), [Markdown](), [OCaml](), [Testing](), [Simulation](), [Verilog]() Tags: [announce](), [documentation](), [fpga](), [hardware](), [libraries](), [markdown](), [ocaml](), [simulation](), [sorting](), [testing]() ### AI overview Jane Street announces a broad set of new Hardcaml libraries, expanded documentation, and improved testing support. The release includes circuit designs, FPGA component bindings, verification tools, simulator backends, Verilog import, and additional simulation and hardware-design utilities. ### Source excerpt I am pleased to announce that we have recently released a slew of new Hardcaml libraries! ## Volumio Motivo: a FOSS Audiophile Experience DevFeed: [Volumio Motivo: a FOSS Audiophile Experience]() Original publisher: [Read original article]() Published: 2019-06-10T00:00:00Z Content type: article Language: en Sources: [Community blog on PINE64]() Topics: [fpga](), [SOC](), [foss](), [Linux](), [interface](), [Software](), [IO](), [USB]() Tags: [audio](), [audioplayer](), [foss](), [fpga](), [interface](), [io](), [linux](), [motivo](), [soc](), [software](), [specifications](), [usability](), [usb](), [volumio]() ### AI overview This article presents the Volumio Motivo, a higher-end audio device powered by the Volumio Linux distribution. It describes Yottamusic's Metaclock design, which uses an A64 SoC, SDIO data transfer, a dedicated FPGA, memory buffering, and DAC communication, and lists reported audio measurements and hardware specifications. ### Source excerpt The higher end alternative to the PRIMO, the MOTIVO, will catch your eye and ear. It is powered by the FOSS audiophile Linux distribution - Volumio - that is aviable for many Single Board computers, including the PINE A64-LTS and the ROCK64. From our point of view, the technology inside the MOTIVO is what makes it stand out, although, we can't argue with its great looks. Powered by a SOPine module, the Volumio Motivo is a true fusion of form and fucntion, and a brainchild of a Joint Venture between world-class industrial design firm Design Narratives and R&D and audio design Company Yottamusic. Yottamusic has been working for 10 years on their the core-technology which is now in the Motivo: METACLOCK. This Technology has 3 core principles: Do not use a generic SOC (which handles communication with the DAC) Use an interface that, other than USB and I2S allows faster data transfer Use a dedicated FPGA to handle communication with the DAC. Therefore emancipating the Audio Quality outcome from the OSCPU combination. It works this way: The audio stream is sent from the A64 SOC via a high-speed BUS (SDIO) to a dedicated FPGA Here the stream is reclocked via a double buffer and stored on a high-speed memory It's then sent, at the right moment to the DAC The results that it brings: 104dB THD+N 110dB SNR Jitter: 200ps Maximum Network data correction This means that with Metaclock technology, Volumio Motivo is able to achieve outstanding sound quality performances without the need of esoteric (and expensive) designs, following Volumio's core principle: the best possible sound quality with an unbeatable priceperformance ratio. Integrating Metaclock technology is being probably the biggest challenge Volumio Team has faced so far: since this technology has never been done before, in this way, there is no standard to follow nor any HOWTO nor literature. Work is currently being done to implement the very complex software integration to take the most out of this technology, without ## How VP9 delivers value for Twitch's esports live streaming DevFeed: [How VP9 delivers value for Twitch's esports live streaming]() Original publisher: [Read original article]() Author: Yueshi Shen Published: 2018-12-19T21:12:17Z Content type: article Language: en Sources: [Twitch]() Topics: [Twitch](), [Compression](), [fpga](), [Streaming](), [Hardware](), [browsers](), [Playback]() Tags: [browsers](), [compression](), [decoding](), [encoding](), [engineering](), [fpga](), [h-264](), [live-streaming](), [streaming](), [twitch](), [videos](), [vp9]() ### AI overview This article explains how Twitch selected FPGA hardware for real-time VP9 encoding of premium esports and partner live streams. It discusses VP9's compression advantages and implementation challenges, and reports at least 25% bitrate savings compared with the highest-quality H.264 encoders used in Twitch's production. ### Source excerpt By: Akrum Elkhazin, Video Algorithm Architect, NGCodec, akrum.elkhazin@ngcodec.com Avinash Ramachandran, Video Software Architect, NGCodec, avinash.ramachandran@ngcodec.com Roshan Baliga, Product Manager, Google, rdb@google.com Jai Krishnan, Product Manager, Google, jaikk@google.com Tarek Amara, Senior Video Specialist, Twitch, amatarek@twitch.tv Alex Converse, Senior Software Engineer, Twitch, alexconv@twitch.tv Yueshi Shen, Principal Research Engineer, Twitch, yshen@twitch.tv Summary: VP9 will soon help Twitch offer a better viewing experience for premium esports and partner channels Video compression is the key to successful delivery of digital video across various applications like broadcast, teleconference, surveillance, and online streaming services. Since 2003 (i.e., 15 years ago), H.264 has been the state-of-the-art video compression format and has enabled HDTV, Blu-ray Disc, Internet video websites (e.g., YouTube, Twitch), and so on. Nevertheless, according to Twitch's recent analysis, H.264 has reached its compression performance limit, particularly for real-time encoding of gaming content at the HD resolution (1080p60). On the other hand, newer-generation video standards, namely VP9, HEVC, and AV1, show significant compression gain, which can bring considerable commercial benefits to content platforms (e.g., offering viewers better video quality, reducing the video loading time and the buffering rate, increasing the customer reach, decreasing the IP transit cost). Currently, although decoding and playback of VP9 video are widely supported on devices and browsers used by Twitch's audience, encoding gaming video content with a high efficiency and real-time performance is a substantial challenge due to the high complexity of VP9. Through a rigorous feasibility study, we have eventually selected FPGA as the hardware platform for real-time VP9 encoding and are deploying it to broadcast our premium eSports and partner channels in the near future (please watch t ## Jane Street extends its OCaml software stack to FPGA applications DevFeed: [Jane Street extends its OCaml software stack to FPGA applications]() Original publisher: [Read original article]() Author: Yaron Minsky Published: 2018-04-04T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [OCaml](), [fpga](), [Software](), [Development](), [Hardware]() Tags: [development](), [fpga](), [hardware](), [ocaml](), [software](), [systems]() ### AI overview Jane Street describes how its software stack has expanded across business needs while remaining largely built in OCaml. The article highlights an extension into FPGA applications that aims to leverage the organization's existing OCaml codebase, tools, libraries, and development practices. ### Source excerpt One of the joys of working at Jane Street for the last 15 or so years has been seeing how our software stack has grown in scope. When I started, I was building pretty narrowly focused systems for doing statistical research on trading strategies, and then building systems for executing those same strategies. ## Hiring an FPGA engineer DevFeed: [Hiring an FPGA engineer]() Original publisher: [Read original article]() Author: Yaron Minsky Published: 2017-08-16T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [fpga](), [Hardware](), [Software](), [Software Engineering](), [OCaml](), [Ethernet](), [networking]() Tags: [ethernet](), [fpga](), [hardware](), [ocaml](), [programming](), [software](), [software-engineering]() ### AI overview Jane Street is hiring an FPGA engineer to design FPGA-based applications and improve internal hardware-design tools. The role combines hardware design, software engineering, high-level synthesis, and testing, using the HardCaml synthesis library for OCaml. ### Source excerpt Jane Street is looking to hire an engineer with experience in both software and hardware design to work on FPGA-based applications, and on tools for creating such applications. ## MIAOW Open Source GPU DevFeed: [MIAOW Open Source GPU]() Original publisher: [Read original article]() Published: 2014-10-20T00:00:00Z Content type: article Language: en Sources: [Front Page on ReactOS Website]() Topics: [GPU](), [fpga]() Tags: [fpga](), [free](), [gpu](), [open-source](), [os](), [react](), [reactos](), [win32](), [winapi]() ### AI overview The article describes a master's project involving the design of a GPU on an FPGA and briefly explains that FPGAs are chips whose digital logic can be modified to change their functionality. ### Source excerpt About a year ago I basically disappeared from the project, showing up only very intermittently to write up snippets of text as requested by the team. The reason was I was ramping up for my master's project, an attempt to put a GPU design on an FPGA. For those of you who do not know what FPGAs are, think of them as chips that you can modify the digital logic on to change its functionality.