# GAA

Published articles for GAA.

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## Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)

DevFeed: [Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur)](<https://devfeed.tech/articles/self-heating-and-parasitics-challenge-multi-tier-cfet-scaling-tu-munich-iit-kanpur-100108.md>)

Original publisher: [Read original article](<https://semiengineering.com/self-heating-and-parasitics-challenge-multi-tier-cfet-scaling-tu-munich-iit-kanpur/>)

Author: Technical Paper Link

Published: 2026-10-26T07:01:24Z

Content type: news

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Electrical engineering and computer science (EECS)](<https://devfeed.tech/topics/electrical-engineering-and-computer-science-eecs.md>)

Tags: [3d-monolithic-cmos](<https://devfeed.tech/tags/3d-monolithic-cmos.md>), [analyze](<https://devfeed.tech/tags/analyze.md>), [back-end](<https://devfeed.tech/tags/back-end.md>), [back-end-of-line](<https://devfeed.tech/tags/back-end-of-line.md>), [beol](<https://devfeed.tech/tags/beol.md>), [cfet](<https://devfeed.tech/tags/cfet.md>), [circuits](<https://devfeed.tech/tags/circuits.md>), [cmos](<https://devfeed.tech/tags/cmos.md>), [complementary-fet](<https://devfeed.tech/tags/complementary-fet.md>), [design](<https://devfeed.tech/tags/design.md>), [devices](<https://devfeed.tech/tags/devices.md>), [distribution](<https://devfeed.tech/tags/distribution.md>), [experimental](<https://devfeed.tech/tags/experimental.md>), [gaa](<https://devfeed.tech/tags/gaa.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [heat](<https://devfeed.tech/tags/heat.md>), [indian-institute-of-technology-kanpur](<https://devfeed.tech/tags/indian-institute-of-technology-kanpur.md>), [mol](<https://devfeed.tech/tags/mol.md>), [multi-tier-stacking](<https://devfeed.tech/tags/multi-tier-stacking.md>), [nanosheet-fet](<https://devfeed.tech/tags/nanosheet-fet.md>), [parasitics](<https://devfeed.tech/tags/parasitics.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [scaling](<https://devfeed.tech/tags/scaling.md>), [self-heating](<https://devfeed.tech/tags/self-heating.md>), [study](<https://devfeed.tech/tags/study.md>), [tcad](<https://devfeed.tech/tags/tcad.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [technical-university-of-munich](<https://devfeed.tech/tags/technical-university-of-munich.md>), [thermal-management](<https://devfeed.tech/tags/thermal-management.md>), [transistor-reliability](<https://devfeed.tech/tags/transistor-reliability.md>), [transistors](<https://devfeed.tech/tags/transistors.md>), [tu-munich](<https://devfeed.tech/tags/tu-munich.md>)

### AI overview

The study examines how self-heating and interconnect parasitics affect multi-tier CFET design. Using TCAD models calibrated to experimental measurements, the researchers compare four-tier and conventional two-tier CFETs. They also simulate self-heating to analyze heat distribution and temperature profiles, and use 3-D CMOS inverter models with full middle-of-line and back-end-of-line interconnects to extract parasitic RC networks. The supplied excerpt does not state the study's quantitative findings.

### Source excerpt

Researchers at the Technical University of Munich and Indian Institute of Technology Kanpur published "Self-Heating and Parasitic Effects in Multi-Tier CFET Design." Abstract Excerpt: "We study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked.... " read more The post Self-Heating And Parasitics Challenge Multi-Tier CFET Scaling (TU Munich, IIT Kanpur) appeared first on Semiconductor Engineering.

## Comparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials)

DevFeed: [Comparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials)](<https://devfeed.tech/articles/comparing-a7-cfet-and-a10-nanosheet-fets-from-parasitics-to-chip-reliability-tum-unimore-applied-materials-60256.md>)

Original publisher: [Read original article](<https://semiengineering.com/comparing-a7-cfet-and-a10-nanosheet-fets-from-parasitics-to-chip-reliability-tum-unimore-applied-materials/>)

Author: Technical Paper Link

Published: 2026-09-25T22:29:43Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Simulation and Design](<https://devfeed.tech/topics/simulation-and-design.md>), [implementation](<https://devfeed.tech/topics/implementation.md>), [3D](<https://devfeed.tech/topics/3d.md>), [Artificial Intelligence](<https://devfeed.tech/topics/ai.md>)

Tags: [2026](<https://devfeed.tech/tags/2026.md>), [a10](<https://devfeed.tech/tags/a10.md>), [a7](<https://devfeed.tech/tags/a7.md>), [advanced-process-nodes](<https://devfeed.tech/tags/advanced-process-nodes.md>), [aging](<https://devfeed.tech/tags/aging.md>), [ai-accelerator](<https://devfeed.tech/tags/ai-accelerator.md>), [ai-accelerators](<https://devfeed.tech/tags/ai-accelerators.md>), [applied-materials](<https://devfeed.tech/tags/applied-materials.md>), [bias-temperature-instability](<https://devfeed.tech/tags/bias-temperature-instability.md>), [bti](<https://devfeed.tech/tags/bti.md>), [cfet](<https://devfeed.tech/tags/cfet.md>), [chip](<https://devfeed.tech/tags/chip.md>), [complementary-fet](<https://devfeed.tech/tags/complementary-fet.md>), [design-verification](<https://devfeed.tech/tags/design-verification.md>), [engineering](<https://devfeed.tech/tags/engineering.md>), [gaa](<https://devfeed.tech/tags/gaa.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [materials](<https://devfeed.tech/tags/materials.md>), [multiphysics](<https://devfeed.tech/tags/multiphysics.md>), [nanosheet-fet](<https://devfeed.tech/tags/nanosheet-fet.md>), [nsfet](<https://devfeed.tech/tags/nsfet.md>), [paper](<https://devfeed.tech/tags/paper.md>), [parasitic-capacitance](<https://devfeed.tech/tags/parasitic-capacitance.md>), [parasitic-resistance](<https://devfeed.tech/tags/parasitic-resistance.md>), [physics](<https://devfeed.tech/tags/physics.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [reliability](<https://devfeed.tech/tags/reliability.md>), [rtl](<https://devfeed.tech/tags/rtl.md>), [rtl-to-gds](<https://devfeed.tech/tags/rtl-to-gds.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [standard-cell](<https://devfeed.tech/tags/standard-cell.md>), [standard-cells](<https://devfeed.tech/tags/standard-cells.md>), [stco](<https://devfeed.tech/tags/stco.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [technical-university-of-munich](<https://devfeed.tech/tags/technical-university-of-munich.md>), [thermal-analysis](<https://devfeed.tech/tags/thermal-analysis.md>), [transistor-scaling](<https://devfeed.tech/tags/transistor-scaling.md>), [transistors](<https://devfeed.tech/tags/transistors.md>), [university-of-modena-and-reggio-emilia](<https://devfeed.tech/tags/university-of-modena-and-reggio-emilia.md>)

### AI overview

A technical paper compares A7 CFET and A10 NSFET technologies using a physics-based system-technology co-evaluation flow. The analysis covers parasitic RC extraction, standard-cell generation, RTL-to-GDS implementation for an AI accelerator, thermal behavior, and BTI aging.

### Source excerpt

Researchers at the TU Munich, University of Modena and Reggio Emilia, and Applied Materials published a technical paper titled "System-Technology Co-Evaluation of A7 CFET and A10 NSFET Technologies from Cell Parasitics to Chip Reliability." Abstract Excerpt: " In this work, we present a physics-based thermal- and aging-aware system-technology co-evaluation (STCO) flow to assess parasitic RCs in... " read more The post Comparing A7 CFET and A10 Nanosheet FETs From Parasitics to Chip Reliability (TUM, UNIMORE, Applied Materials) appeared first on Semiconductor Engineering.