# gaafet

Published articles for gaafet.

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## UCSC researchers explore backside clock meshes for 2 nm GAAFET technology

DevFeed: [UCSC researchers explore backside clock meshes for 2 nm GAAFET technology](<https://devfeed.tech/articles/backside-clock-meshes-cut-skew-and-power-in-2nm-nanosheets-ucsc-64920.md>)

Original publisher: [Read original article](<https://semiengineering.com/backside-clock-meshes-cut-skew-and-power-in-2nm-nanosheets-ucsc/>)

Author: Technical Paper Link

Published: 2026-10-05T18:07:21Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [ddr5](<https://devfeed.tech/topics/ddr5.md>), [LaTeX](<https://devfeed.tech/topics/latex.md>)

Tags: [2-nm](<https://devfeed.tech/tags/2-nm.md>), [backside-clock-meshes](<https://devfeed.tech/tags/backside-clock-meshes.md>), [backside-power-delivery](<https://devfeed.tech/tags/backside-power-delivery.md>), [backside-power-delivery-network](<https://devfeed.tech/tags/backside-power-delivery-network.md>), [bspdn](<https://devfeed.tech/tags/bspdn.md>), [buried-power-rails](<https://devfeed.tech/tags/buried-power-rails.md>), [chip](<https://devfeed.tech/tags/chip.md>), [clock-distribution](<https://devfeed.tech/tags/clock-distribution.md>), [clock-mesh](<https://devfeed.tech/tags/clock-mesh.md>), [design-space-exploration](<https://devfeed.tech/tags/design-space-exploration.md>), [design-verification](<https://devfeed.tech/tags/design-verification.md>), [gaafet](<https://devfeed.tech/tags/gaafet.md>), [gate-all-around](<https://devfeed.tech/tags/gate-all-around.md>), [gt2n](<https://devfeed.tech/tags/gt2n.md>), [hspice](<https://devfeed.tech/tags/hspice.md>), [nanosheet-transistors](<https://devfeed.tech/tags/nanosheet-transistors.md>), [nanosheets](<https://devfeed.tech/tags/nanosheets.md>), [openroad](<https://devfeed.tech/tags/openroad.md>), [paper](<https://devfeed.tech/tags/paper.md>), [performance](<https://devfeed.tech/tags/performance.md>), [physical-design](<https://devfeed.tech/tags/physical-design.md>), [power-delivery](<https://devfeed.tech/tags/power-delivery.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [routing](<https://devfeed.tech/tags/routing.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [through-silicon-vias](<https://devfeed.tech/tags/through-silicon-vias.md>), [transistors](<https://devfeed.tech/tags/transistors.md>), [tsv](<https://devfeed.tech/tags/tsv.md>), [uc-santa-cruz](<https://devfeed.tech/tags/uc-santa-cruz.md>), [university-of-california-santa-cruz](<https://devfeed.tech/tags/university-of-california-santa-cruz.md>)

### AI overview

University of California, Santa Cruz researchers report a design-space exploration of backside clock meshes for 2 nm GAAFET technology. Their paper examines using available backside metal layers for clock distribution, with connections to frontside flip-flops made through through-silicon vias.

### Source excerpt

Researchers at the University of California, Santa Cruz published a technical paper titled "Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology." Abstract Excerpt: "Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power... " read more The post Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC) appeared first on Semiconductor Engineering.