# icelake

Published articles for icelake.

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## Ice Lake AVX-512 Downclocking

DevFeed: [Ice Lake AVX-512 Downclocking](<https://devfeed.tech/articles/ice-lake-avx-512-downclocking-28490.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/08/19/icl-avx512-freq.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-08-19T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [intel](<https://devfeed.tech/topics/intel.md>), [floating-point](<https://devfeed.tech/topics/floating-point.md>), [Rocket](<https://devfeed.tech/topics/rocket.md>)

Tags: [avx](<https://devfeed.tech/tags/avx.md>), [avx512](<https://devfeed.tech/tags/avx512.md>), [blog](<https://devfeed.tech/tags/blog.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [floating-point](<https://devfeed.tech/tags/floating-point.md>), [icelake](<https://devfeed.tech/tags/icelake.md>), [intel](<https://devfeed.tech/tags/intel.md>), [performance](<https://devfeed.tech/tags/performance.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This technical post investigates AVX2- and AVX-512-related license-based downclocking on Intel Ice Lake and Rocket Lake CPUs. Measurements from an Ice Lake i5-1035G4 indicate little frequency reduction from wider instructions, with a reported 100 MHz decrease in one single-core case.

### Source excerpt

Examining the extent of AVX related downclocking on Intel's Ice Lake CPU

## Ice Lake Store Elimination

DevFeed: [Ice Lake Store Elimination](<https://devfeed.tech/articles/ice-lake-store-elimination-28487.md>)

Original publisher: [Read original article](<https://travisdowns.github.io/blog/2020/05/18/icelake-zero-opt.html>)

Author: Travis Downs (travis.downs@gmail.com)

Published: 2020-05-18T00:00:00Z

Content type: article

Language: en

Sources: [Performance Matters](<https://devfeed.tech/sources/performance-matters.md>)

Topics: [intel](<https://devfeed.tech/topics/intel.md>), [Optimization](<https://devfeed.tech/topics/optimization.md>), [x86](<https://devfeed.tech/topics/x86.md>), [Compiler](<https://devfeed.tech/topics/compiler.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>)

Tags: [analysis](<https://devfeed.tech/tags/analysis.md>), [avx](<https://devfeed.tech/tags/avx.md>), [blog](<https://devfeed.tech/tags/blog.md>), [compiler](<https://devfeed.tech/tags/compiler.md>), [icelake](<https://devfeed.tech/tags/icelake.md>), [intel](<https://devfeed.tech/tags/intel.md>), [optimization](<https://devfeed.tech/tags/optimization.md>), [performance](<https://devfeed.tech/tags/performance.md>), [uarch](<https://devfeed.tech/tags/uarch.md>), [x86](<https://devfeed.tech/tags/x86.md>)

### AI overview

This article analyzes zero-store optimization on Intel's Ice Lake architecture. It compares performance results across memory regions and examines how compiler-generated 512-bit versus 256-bit instructions, including AVX-512 clocking effects, influence the observed behavior.

### Source excerpt

We look at the zero store optimization as it applies to Intel's newest micro-architecture.