# l2 cache

Published articles for l2 cache.

This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles.

## Efinix Sapphire RV64 SoC - Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs

DevFeed: [Efinix Sapphire RV64 SoC - Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs](<https://devfeed.tech/articles/efinix-sapphire-rv64-soc-configurable-risc-v-soft-cores-with-ddr3-lpddr4x-and-hyperram-for-efinix-fpgas-76973.md>)

Original publisher: [Read original article](<https://www.cnx-software.com/2026/10/08/efinix-sapphire-rv64-soc-configurable-risc-v-soft-cores-with-ddr3-lpddr4x-and-hyperram-for-efinix-fpgas/>)

Author: Debashis Das

Published: 2026-10-08T00:00:32Z

Content type: news

Language: en

Sources: [CNX Software - Embedded Systems News](<https://devfeed.tech/sources/cnx-software-embedded-systems-news.md>)

Topics: [Embedded Systems](<https://devfeed.tech/topics/embedded-systems.md>), [RISC-V](<https://devfeed.tech/topics/riscv.md>), [fpga](<https://devfeed.tech/topics/fpga.md>), [Intel Core](<https://devfeed.tech/topics/intel-core.md>)

Tags: [c](<https://devfeed.tech/tags/c.md>), [c-plus-plus](<https://devfeed.tech/tags/c-plus-plus.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [efinix](<https://devfeed.tech/tags/efinix.md>), [embedded](<https://devfeed.tech/tags/embedded.md>), [fpga](<https://devfeed.tech/tags/fpga.md>), [fpgas](<https://devfeed.tech/tags/fpgas.md>), [fpu](<https://devfeed.tech/tags/fpu.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [i2c](<https://devfeed.tech/tags/i2c.md>), [l2-cache](<https://devfeed.tech/tags/l2-cache.md>), [risc-v](<https://devfeed.tech/tags/risc-v.md>), [soc](<https://devfeed.tech/tags/soc.md>), [software](<https://devfeed.tech/tags/software.md>), [spi](<https://devfeed.tech/tags/spi.md>), [system](<https://devfeed.tech/tags/system.md>)

### AI overview

Efinix introduced Sapphire RV64, a configurable 64-bit RISC-V soft-core SoC for its FPGA devices. It supports one to four cores, memory options including DDR3, LPDDR4x, and HyperRAM, and configurable cache, I/O, and debugging features. The article also describes software tools for configuring the core and developing C/C++ firmware.

### Source excerpt

Efinix has introduced the Sapphire RV64 SoC, a configurable 64-bit RISC-V soft-core processor designed for its Titanium and Trion FPGAs. It is based on the VexiiRiscv core and can be configured with one to four RISC-V cores running at up to 400 MHz. The Sapphire RV64 has a seven-stage pipeline, configurable L1 caches, optional 64-512 KB L2 cache, and 4-512 KB of on-chip RAM. It supports DDR3, LPDDR4x, and HyperRAM with up to 512-bit AXI interfaces and external memory from 4 MB to 8 GB. Other features include an optional FPU, branch predictor, prefetchers, SV39 MMU, up to 32 GPIOs, five I²C, three SPI, three UARTs, timers, watchdog, and up to eight user interrupts. Efinix Sapphire RV64 SoC specifications: CPU 1 to 4x VexiiRiscv 64-bit cores with a 7-stage pipeline (fetch, align-decompress, decode, issue, execute, memory, and writeback) Configurable system clock frequency from 20 MHz to 400 MHz Supports RV64IMACFD_Zba_Zbc_Zbs extensions [...] The post Efinix Sapphire RV64 SoC - Configurable RISC-V soft-cores with DDR3, LPDDR4x, and HyperRAM for Efinix FPGAs appeared first on CNX Software - Embedded Systems News.

## Qualcomm's System Level Architecture in the Snapdragon X2 Elite

DevFeed: [Qualcomm's System Level Architecture in the Snapdragon X2 Elite](<https://devfeed.tech/articles/qualcomm-s-system-level-architecture-in-the-snapdragon-x2-elite-61975.md>)

Original publisher: [Read original article](<https://chipsandcheese.com/p/qualcomms-system-level-architecture>)

Author: Chester Lam

Published: 2026-09-29T16:07:30Z

Content type: article

Language: en

Sources: [Chips and Cheese](<https://devfeed.tech/sources/chips-and-cheese.md>)

Topics: [software-architecture](<https://devfeed.tech/topics/software-architecture.md>), [Chip design](<https://devfeed.tech/topics/chip-design.md>)

Tags: [cache](<https://devfeed.tech/tags/cache.md>), [chips](<https://devfeed.tech/tags/chips.md>), [compute](<https://devfeed.tech/tags/compute.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [dram](<https://devfeed.tech/tags/dram.md>), [geforce](<https://devfeed.tech/tags/geforce.md>), [interconnect](<https://devfeed.tech/tags/interconnect.md>), [l2-cache](<https://devfeed.tech/tags/l2-cache.md>), [latency](<https://devfeed.tech/tags/latency.md>), [low-latency](<https://devfeed.tech/tags/low-latency.md>), [performance](<https://devfeed.tech/tags/performance.md>), [pipeline](<https://devfeed.tech/tags/pipeline.md>), [qualcomm](<https://devfeed.tech/tags/qualcomm.md>), [snapdragon](<https://devfeed.tech/tags/snapdragon.md>), [snapdragon-x2](<https://devfeed.tech/tags/snapdragon-x2.md>), [snapdragon-x2-elite](<https://devfeed.tech/tags/snapdragon-x2-elite.md>)

### AI overview

The article examines the system-level architecture of Qualcomm's Snapdragon X2 Elite Extreme laptop chip. It describes how six-core clusters, shared L2 caches and the interconnect help manage bandwidth, latency and the number of clients, and reports measured L2 latency and bandwidth characteristics. Some explanations for observed latency differences are presented as the author's hypotheses.

### Source excerpt

Laptop chips have gotten very powerful in recent years, with increasing CPU core counts, more powerful iGPUs, and higher DRAM bandwidth to feed that compute.

## How did AMD Ryzen get 50% faster in two years?

DevFeed: [How did AMD Ryzen get 50% faster in two years?](<https://devfeed.tech/articles/how-did-amd-ryzen-get-50-faster-in-two-years-55112.md>)

Original publisher: [Read original article](<https://lemire.me/blog/2026/09/18/how-did-amd-ryzen-get-50-faster-in-two-years/>)

Author: Daniel Lemire

Published: 2026-09-18T17:26:04Z

Content type: article

Language: en

Sources: [Daniel Lemire](<https://devfeed.tech/sources/daniel-lemire.md>)

Topics: [cpu](<https://devfeed.tech/topics/cpu.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [Parallelism](<https://devfeed.tech/topics/parallelism.md>), [Cache](<https://devfeed.tech/topics/cache.md>)

Tags: [2022](<https://devfeed.tech/tags/2022.md>), [3d](<https://devfeed.tech/tags/3d.md>), [amd](<https://devfeed.tech/tags/amd.md>), [core](<https://devfeed.tech/tags/core.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [desktop](<https://devfeed.tech/tags/desktop.md>), [epyc](<https://devfeed.tech/tags/epyc.md>), [geekbench](<https://devfeed.tech/tags/geekbench.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [l2-cache](<https://devfeed.tech/tags/l2-cache.md>), [l3-cache](<https://devfeed.tech/tags/l3-cache.md>), [performance](<https://devfeed.tech/tags/performance.md>), [processor](<https://devfeed.tech/tags/processor.md>), [processors](<https://devfeed.tech/tags/processors.md>), [ryzen](<https://devfeed.tech/tags/ryzen.md>), [science-and-technology](<https://devfeed.tech/tags/science-and-technology.md>), [september-2026](<https://devfeed.tech/tags/september-2026.md>), [simd](<https://devfeed.tech/tags/simd.md>), [venice](<https://devfeed.tech/tags/venice.md>)

### AI overview

The article compares AMD Ryzen 7 processors from 2022 to 2024 and explains how architectural changes produced roughly 50% higher Geekbench 6 performance. It highlights wider instruction dispatch, larger caches, more arithmetic units, a larger reorder buffer, and wider SIMD units, then briefly discusses AMD's planned 256-core Epyc Venice processor.

### Source excerpt

People still tell me that CPUs are boring. That nothing much happens anymore. Let us look at AMD Ryzen 7 processors from 2022 to 2024: the 5800X3D (Zen 3), the 7800X3D (Zen 4) and the 9800X3D (Zen 5). They are comparable 8-core chips with 3D V-Cache. I have written about them before, in How stagnant ... Continue reading How did AMD Ryzen get 50% faster in two years?

## How To Smash The Memory Wall Plaguing High Performance Systems

DevFeed: [How To Smash The Memory Wall Plaguing High Performance Systems](<https://devfeed.tech/articles/how-to-smash-the-memory-wall-plaguing-high-performance-systems-48028.md>)

Original publisher: [Read original article](<https://www.nextplatform.com/store/2026/09/16/how-to-smash-the-memory-wall-plaguing-high-performance-systems/5296866>)

Author: Cristian Vasile

Published: 2026-09-16T13:37:11Z

Content type: tutorial

Language: en

Sources: [The Next Platform: In-depth coverage of high end computing](<https://devfeed.tech/sources/the-next-platform-in-depth-coverage-of-high-end-computing.md>)

Topics: [systems](<https://devfeed.tech/topics/systems.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [data](<https://devfeed.tech/topics/data.md>), [Cache](<https://devfeed.tech/topics/cache.md>), [Computing](<https://devfeed.tech/topics/computing.md>), [parquet](<https://devfeed.tech/topics/parquet.md>), [Algorithms](<https://devfeed.tech/topics/algorithms.md>), [computational complexity](<https://devfeed.tech/topics/computational-complexity.md>), [The Chapel Parallel Programming Language](<https://devfeed.tech/topics/chapel.md>)

Tags: [architecture](<https://devfeed.tech/tags/architecture.md>), [cache](<https://devfeed.tech/tags/cache.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [distributed](<https://devfeed.tech/tags/distributed.md>), [high-performance](<https://devfeed.tech/tags/high-performance.md>), [l2-cache](<https://devfeed.tech/tags/l2-cache.md>), [l3-cache](<https://devfeed.tech/tags/l3-cache.md>), [latency](<https://devfeed.tech/tags/latency.md>), [memory](<https://devfeed.tech/tags/memory.md>), [parallel](<https://devfeed.tech/tags/parallel.md>), [parquet](<https://devfeed.tech/tags/parquet.md>), [performance](<https://devfeed.tech/tags/performance.md>), [store](<https://devfeed.tech/tags/store.md>)

### AI overview

The article examines memory and cache-performance bottlenecks in high-performance systems processing large analytical datasets. It proposes exploring Z-Order (Morton Layout) memory addressing as an alternative to linear RAM addressing and uses AMD's Turin Epyc 9005 architecture as a theoretical baseline.

### Source excerpt

In my day-to-day work, I process massive data volumes, wrestling with large-scale .parquet files, co ...