# Lam Research Published articles for Lam Research. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Chip Scaling Moves Beyond The Transistor DevFeed: [Chip Scaling Moves Beyond The Transistor]() Original publisher: [Read original article]() Author: Gregory Haley Published: 2026-10-22T07:05:16Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design](), [Electrical engineering and computer science (EECS)]() Tags: [2](), [2023](), [2026](), [3](), [advanced](), [advanced-packaging](), [advantest](), [agentic-ai](), [ai](), [amkor](), [ase](), [chip](), [chiplets](), [co-packaged-optics](), [conversations](), [cpo](), [digital-twins](), [engineering](), [ev-group](), [hbm](), [heterogeneous-integration](), [imec](), [inspection](), [intel](), [intel-foundry](), [known-good-assembly](), [known-good-die](), [lam-research](), [manufacturing-packaging-and-materials](), [marvell](), [metrology](), [microtronic](), [optical-interconnects](), [packaging](), [photonics](), [power-delivery](), [scaling](), [semi](), [semicon](), [semicon-west](), [semicon-west-2026](), [semiconductor](), [semiconductor-engineering](), [semiconductor-manufacturing](), [semiconductor-test](), [silicon-photonics](), [test](), [top-stories](), [transistor]() ### AI overview Semiconductor scaling is becoming a system-level challenge: performance and manufacturability depend on coordinating silicon, packaging, memory, interconnects, power, cooling, test, and software. The article describes advanced packaging as part of system architecture, while larger heterogeneous assemblies raise yield, reliability, cost, inspection, and traceability demands. Photonics moving closer to compute adds alignment, metrology, and optical test requirements that must reach semiconductor manufacturing throughput; some assembly processes are difficult to rework. AI is already used in design and manufacturing, and agentic systems can explore parameter spaces too large for manual search, but letting them change recipes or make production decisions raises questions about human approval and evidence. The industry's task is to combine these technologies repeatedly, reliably, and economically at volume. ### Source excerpt SEMICON West 2026: Advanced packaging, photonics, test, and AI are increasingly intertwined; very different conversations ahead. The post Chip Scaling Moves Beyond The Transistor appeared first on Semiconductor Engineering. ## How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å DevFeed: [How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å]() Original publisher: [Read original article]() Author: Qingpeng Wang Published: 2026-10-22T07:05:02Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design]() Tags: [3d](), [a7](), [architecture](), [architectures](), [area](), [blogs-md](), [cfet](), [channel](), [channel-width](), [cmos](), [complementary-fet](), [effective](), [electrostatics](), [gate-all-around](), [lam-research](), [logic](), [manufacturing-packaging-and-materials](), [perfecting-the-process](), [performance](), [process](), [scaling](), [self-aligned](), [semiconductor](), [sequence](), [sram](), [technology]() ### AI overview The proposed self-aligned CFET (SA-CFET) stacks NMOS and PMOS devices vertically and uses self-aligned buried power rail, contact, and through-silicon-via modules to address contact crowding and overlay sensitivity. SEMulator3D digital-twin process modeling demonstrated 6T SRAM and logic cells, including NOT, NAND, and NOR, with a modeled SRAM bit cell area of 0.0094 μm²--52.7% smaller than N3 and 19% smaller than cited A7 CFET designs. The excerpt also reports at least a 10 nm overlay window across critical contact layers without modeled open or short failures. The authors say the design maintains N3 specifications and may support scaling at 10 Å and beyond; these are simulation results and a proposed scaling path, not reported fabrication results. ### Source excerpt A process sequence for SRAM and logic that delivers higher performance through larger effective channel width and improved electrostatics at smaller nodes. The post How Self-Aligned CFET Technology Could Extend CMOS Scaling Beyond 10 Å appeared first on Semiconductor Engineering. ## SK hynix reportedly offers to build a NAND fab in the US if Washington lets it expand in China DevFeed: [SK hynix reportedly offers to build a NAND fab in the US if Washington lets it expand in China]() Original publisher: [Read original article]() Author: Skye Jacobs Published: 2026-10-16T11:58:00Z Content type: news Language: en Sources: [TechSpot]() Topics: [DRAM price increase](), [nand flash price increase](), [networking hardware prices]() Tags: [applied-materials](), [china](), [computex-2026](), [data-center](), [data-centers](), [exports](), [factory](), [flash](), [flash-memory](), [hardware](), [industry](), [lam-research](), [let](), [manufacturing](), [manufacturing-technology](), [nand](), [politics](), [sk-hynix](), [united-states](), [us]() ### AI overview SK hynix is reportedly proposing a US NAND fab in exchange for US approval to send more chipmaking equipment to its Dalian plant in China. Solidigm says it has buyers for all the SSDs it produces, and added tools in unused factory space could increase output. The equipment requests remain unapproved, while the US fab is still a proposal. ### Source excerpt The equipment would go into unused space in Dalian's Mod B building. Completed in 2023, the building was never fully equipped because of the memory market downturn. Some tools are installed, but much of the space remains available. Read Entire Article ## Shift Left Complicates Fab Data Management DevFeed: [Shift Left Complicates Fab Data Management]() Original publisher: [Read original article]() Author: Anne Meixner and Laura Peters Published: 2026-10-08T07:02:25Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [data-engineering](), [data-architecture](), [Feature Engineering](), [AI Chat]() Tags: [advanced-process-control](), [ai-ml-inference](), [apc](), [data](), [data-management](), [data-veracity](), [data-volume](), [digital-twins](), [engineering](), [equipment-sensors](), [intel-foundry](), [lam-research](), [onto-innovation](), [pdf-solutions](), [semiconductor](), [shift-left](), [siemens-eda](), [streaming](), [synopsys](), [test-measurement-and-analytics](), [top-stories](), [virtual-twins](), [yield]() ### AI overview Semiconductor fabs are using high-resolution equipment sensor data and AI/ML inference to detect yield problems earlier and improve in-situ process control. The resulting growth in data volume and speed creates infrastructure and data-management challenges. Fabs must preserve context and traceability across process modules so that siloed local optimization does not undermine cross-fab analytics and model quality. ### Source excerpt Streaming sensor data creates new challenges for advanced process control. The post Shift Left Complicates Fab Data Management appeared first on Semiconductor Engineering. ## One Substrate No Longer Rules Them All DevFeed: [One Substrate No Longer Rules Them All]() Original publisher: [Read original article]() Author: Gregory Haley Published: 2026-09-28T07:01:09Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design](), [AI Infrastructure]() Tags: [advanced-packaging](), [amkor](), [applied-materials](), [brewer-science](), [bridges](), [capacity](), [chip](), [chiplets](), [executive](), [glass-substrates](), [intel-foundry](), [interconnect](), [interposers](), [lam-research](), [layers](), [limits](), [manufacturing-packaging-and-materials](), [matching](), [material](), [materials](), [mitsubishi-chemical-group](), [osats](), [package-architecture](), [power-delivery](), [prismark](), [process](), [scaling](), [semiconductor](), [server](), [servers](), [shinko-electric](), [silicon](), [substrates](), [synopsys](), [top-stories]() ### AI overview Advanced package substrates are becoming application-specific as larger package bodies, more layers, finer routing, and embedded functions raise capability requirements. In AI and server packages, rising substrate value reflects greater material use and structure, while capacity alone does not ensure a supplier can meet a package's materials, dimensions, and process limits. ### Source excerpt Larger packages, finer routing, and embedded functions are pushing advanced substrates toward application-specific designs. The post One Substrate No Longer Rules Them All appeared first on Semiconductor Engineering. ## How Robotics And Intelligent Equipment Control Drive Next-Gen Fab Productivity DevFeed: [How Robotics And Intelligent Equipment Control Drive Next-Gen Fab Productivity]() Original publisher: [Read original article]() Author: Laura Peters Published: 2026-09-21T07:01:36Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Robotics](), [Automation](), [Artificial Intelligence](), [Computing](), [autonomous vehicles]() Tags: [acoustic-inspection](), [ai](), [automation](), [autonomous-robot](), [boosting](), [cobot](), [computing](), [equipment-control](), [intel-foundry](), [lam-research](), [manufacturing-packaging-and-materials](), [microtronic](), [pdf-solutions](), [preventive-maintenance](), [robotics](), [thermal-inspection](), [tool-fingerprinting](), [tool-to-tool-matching](), [top-stories](), [umc](), [uptime](), [visual-inspection](), [yield]() ### AI overview The article describes how robotics, automation, AI, and equipment-control systems improve semiconductor-fab productivity by increasing repeatability, uptime, and yield. It also explains how connected material, equipment, and wafer data helps engineers detect variation, enforce operating limits, and prevent processing problems. ### Source excerpt Behind the scenes, advanced equipment control and robotics are enabling higher levels of repeatability, tool uptime, and yield. The post How Robotics And Intelligent Equipment Control Drive Next-Gen Fab Productivity appeared first on Semiconductor Engineering. ## Virtual Fabrication Meets Stress Physics: Solving GAA Channel Non-Uniformity DevFeed: [Virtual Fabrication Meets Stress Physics: Solving GAA Channel Non-Uniformity]() Original publisher: [Read original article]() Author: Swapnil Kailash More Published: 2026-09-17T07:04:20Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Simulation and Design](), [Optimization]() Tags: [blogs-md](), [channel-width](), [engineering](), [etch](), [gaa-fets](), [gate-all-around](), [lam-research](), [manufacturing-packaging-and-materials](), [mechanical-stress](), [nanosheets](), [perfecting-the-process](), [physics](), [process-modeling](), [semiconductor](), [semiconductor-manufacturing](), [virtual-fabrication]() ### AI overview The article explains how non-uniform mechanical stress across stacked nanosheet channels in gate-all-around transistors affects carrier mobility, current flow, threshold voltage, and leakage. It describes using SEMulator3D stress modeling to identify process variations and optimize channel thickness, fin width, and lateral etch, including a finding that a slightly thicker top channel improves stress uniformity. ### Source excerpt Even small imbalances between stacked nanosheets can distort device behavior in ways that are difficult to predict from geometry alone. The post Virtual Fabrication Meets Stress Physics: Solving GAA Channel Non-Uniformity appeared first on Semiconductor Engineering.