# NanoIC Pilot Line

Published articles for NanoIC Pilot Line.

This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles.

## Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations

DevFeed: [Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations](<https://devfeed.tech/articles/advancing-the-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell-configurations-65547.md>)

Original publisher: [Read original article](<https://semiengineering.com/advancing-the-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell-configurations-2/>)

Author: Geert Hellings

Published: 2026-10-06T07:01:13Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [fpga](<https://devfeed.tech/topics/fpga.md>), [ddr5](<https://devfeed.tech/topics/ddr5.md>)

Tags: [cfet](<https://devfeed.tech/tags/cfet.md>), [cfets](<https://devfeed.tech/tags/cfets.md>), [chip](<https://devfeed.tech/tags/chip.md>), [complementary-fet](<https://devfeed.tech/tags/complementary-fet.md>), [design-technology-co-optimization](<https://devfeed.tech/tags/design-technology-co-optimization.md>), [dtco](<https://devfeed.tech/tags/dtco.md>), [imec](<https://devfeed.tech/tags/imec.md>), [manufacturing-packaging-and-materials](<https://devfeed.tech/tags/manufacturing-packaging-and-materials.md>), [nanoic-pilot-line](<https://devfeed.tech/tags/nanoic-pilot-line.md>), [perspectives-analysis](<https://devfeed.tech/tags/perspectives-analysis.md>), [routability](<https://devfeed.tech/tags/routability.md>), [sram](<https://devfeed.tech/tags/sram.md>), [standard-cell](<https://devfeed.tech/tags/standard-cell.md>), [standard-cells](<https://devfeed.tech/tags/standard-cells.md>), [the-imec-report](<https://devfeed.tech/tags/the-imec-report.md>), [transistors](<https://devfeed.tech/tags/transistors.md>)

### AI overview

The article describes imec's double-flip sequential CFET architecture, which supports both split-gate and common-gate configurations and is reported to achieve up to 98% standard-cell layout efficiency. It also presents a 5T+1 CFET SRAM bit cell with a reported 12.5% smaller area and 7-15% faster write operation than a conventional 6T CFET SRAM cell, along with a design-technology co-optimization study showing improved back-end-of-line routability for A7 CFET designs.

### Source excerpt

Part 2: Toward scalable sCFET standard cell architectures: split-gate devices, a 5T+1 CFET SRAM bit cell, and improved back-end-of-line routability. The post Advancing The CFET-Based Device Roadmap: Novel Integration Modules And Standard Cell Configurations appeared first on Semiconductor Engineering.