# packaging Published articles for packaging. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## EE Times Magazine - November 2026 DevFeed: [EE Times Magazine - November 2026]() Original publisher: [Read original article]() Author: Anne-Françoise Pelé Published: 2026-11-05T22:30:00Z Content type: news Language: en Sources: [EE Times]() Topics: [Chip design](), [Quantum Computing](), [AI Research](), [Internet of things](), [autonomous vehicles]() Tags: [2026](), [3d](), [advanced](), [advanced-packaging](), [agriculture](), [ai](), [analog](), [analysis](), [applied-materials](), [asm](), [autonomous](), [autonomous-driving](), [autonomy](), [business](), [canada](), [capacity](), [capital](), [chip-manufacturing](), [community](), [designline](), [digital](), [digital-magazine](), [education](), [ee](), [ee-times](), [ee-times-university](), [eelife](), [eelive-electronic-design](), [eet](), [electrical-engineering](), [electronic-components](), [electronic-engineering-times](), [electronics](), [embedded-systems](), [emerging-technologies](), [farm](), [fundamentals-courses](), [learning](), [manufacturing](), [mixed-signal](), [news](), [november-2026](), [opinion](), [packaging](), [part-search](), [product-search](), [robotics](), [semiconductor](), [semiconductor-manufacturing](), [semiconductors](), [smart-farming](), [software](), [tech-papers](), [technology](), [video]() ### AI overview The November 2026 edition covers semiconductor manufacturing and packaging, farm autonomy, and Canada's efforts to commercialize emerging technologies. It highlights Applied Materials' $5 billion EPIC Center, ASM International's work on 3D structures, and a Fraunhofer-IMS nanofabrication partnership. Its farm autonomy report describes sensing, embedded computing, connectivity, and AI used to monitor machinery, irrigation, crop health, and other operations in real time. It examines unresolved barriers including machine safety, rural connectivity, processing capacity, and equipment costs, and considers edge AI and quantum sensing. A report on Canada surveys quantum computing, photonics, advanced materials, and ocean electronics, while identifying capital, talent, infrastructure, and commercialization as persistent obstacles to moving research into domestic production. ### Source excerpt This edition of EE Times Magazine explores advances in semiconductor manufacturing and packaging, farm autonomy, and Canada's efforts to commercialize emerging technologies. The post EE Times Magazine - November 2026 appeared first on EE Times. ## Hybrid LLM-Deterministic Pipelines for Enterprise-Scale Code Migration at Bloomberg DevFeed: [Hybrid LLM-Deterministic Pipelines for Enterprise-Scale Code Migration at Bloomberg]() Original publisher: [Read original article]() Author: Mario Corchero, David Williams, Laszlo Kiss Kollar, Haowen Liu, Shivam Bairoliya, Gala Malbasic, Serkan Kirbas, Federica Sarro Published: 2026-11-05T05:00:00Z Content type: article Language: en Sources: [arXiv: Artificial Intelligence](), [arXiv: Software Engineering]() Topics: [AI Integration Strategies](), [Large Language Model](), [CI/CD](), [Pull Request](), [observability pipelines]() Tags: [bloomberg](), [build-system](), [c-plus-plus](), [code](), [cs-ai](), [cs-se](), [enterprise](), [hybrid](), [llm](), [migration](), [packaging](), [pipelines](), [pull-requests](), [python](), [repositories](), [runtime](), [scale](), [scaling](), [telemetry](), [test](), [testing](), [validation]() ### AI overview Bloomberg's Automated Uplift initiative applied hybrid LLM and deterministic pipelines to two code migration campaigns: Python packaging across about 1,900 candidate repositories and a C++ build system migration across about 6,700. They generated 2,333 pull requests, with 729 successful migrations. The pipeline maximized deterministic processing, limiting the LLM to bounded file transformations using precomputed context, and incorporated production telemetry such as execution logs and usage traces. The abstract identifies review, testing, and deployment by repository owners as the main bottleneck, rather than migration generation. Pipeline verification before opening pull requests reduced these costs in the C++ campaign, where compilation and tests could be checked; fixes also carried over more readily across the more uniform repository population. The evidence here is the paper's abstract. ### Source excerpt arXiv:2611.05457v1 Announce Type: new Abstract: Large organizations carry a long tail of infrastructure migrations that are worth doing but rarely urgent enough to compete with feature work, because each one costs significant engineering time per repository. This paper reports on our industrial experience from Automated Uplift, a multi-month initiative applying LLM-assisted migration pipelines across thousands of Bloomberg repositories. We examine two distinct production campaigns: a heterogeneous Python packaging migration (approx. 1,900 candidate repositories) and a uniform C++ build system migration (approx. 6,700 candidate repositories). Together, these campaigns generated 2,333 pull requests, resulting in 729 successful migrations. We detail our hybrid architectural solution which maximizes deterministic processing, confines the LLM to bounded file transformations within a pre-computed context, and incorporates runtime production telemetry (such as execution logs and usage traces). Our findings show that generating migrations turned out to be the easier part; the bottleneck was the cost, for owning teams, of reviewing, testing, and deploying them. These costs were lowered when changes could be verified directly in the pipeline before opening a PR (as with C++ compilation and test validation), and when the population was uniform enough for fixes to carry over from one repository to the next. We conclude by distilling our experience and findings into actionable, transferable patterns for architecting hybrid LLM-deterministic pipelines and scaling code migrations across the enterprise ## AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE) DevFeed: [AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-11-02T21:08:45Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Image processing](), [Image](), [Chip design]() Tags: [abstract](), [advanced](), [advanced-packaging](), [advanced-semiconductor-engineering](), [ai](), [analysis](), [ase](), [based](), [challenges](), [complexity](), [defect-inspection](), [defects](), [detection](), [devices](), [enhancement](), [failure](), [failure-analysis](), [flip-chip](), [image](), [image-enhancement](), [interconnect](), [interconnects](), [low-k-dielectrics](), [materials-center-leoben](), [packaging](), [pva-tepla](), [sam](), [scanning-acoustic-microscopy](), [semiconductor-manufacturing](), [technical-papers](), [test-measurement-analytics-tech-papers](), [white-bumps]() ### AI overview Researchers from Materials Center Leoben, PVA TePla and ASE propose an AI-based image-enhancement workflow tailored to scanning acoustic microscopy (SAM) images. The goal is to improve detection of cracks in extreme low-K layers of flip-chips, known as "white bumps," which the excerpt says are challenging to detect with traditional failure-analysis methods as semiconductor devices become smaller and more complex. The excerpt does not describe the workflow's implementation or report performance results. ### Source excerpt Researchers at Materials Center Leoben, PVA TePla, and Advanced Semiconductor Engineering (ASE) published "AI-Based Image Enhancement Improves Detection of Interconnect Defects in Microelectronic Packaging." Abstract Excerpt: "Traditional failure-analysis (FA) methods face growing challenges due to the increasing miniaturization and complexity of modern semiconductor devices. In particular, the detection of cracks in the extreme low K... " read more The post AI Image Enhancement Improves Detection Of Flip-Chip Interconnect Defects (MCL, PVA TePla, ASE) appeared first on Semiconductor Engineering. ## 3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB) DevFeed: [3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-11-02T20:00:12Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design](), [Green Software]() Tags: [2-5d](), [3d](), [3d-integration](), [abstract](), [advanced-packaging](), [ai](), [ai-accelerators](), [ai-workloads](), [carbon](), [change](), [chiplets](), [climate](), [climate-change](), [compute](), [compute-resources](), [data](), [embodied-emissions](), [emissions](), [gpu](), [gpus](), [hbm](), [heterogeneous-integration](), [high-bandwidth-memory](), [imec](), [imec-netzero](), [impact](), [integration](), [packaging](), [scaling](), [semiconductor-sustainability](), [technical-papers](), [vrije-universiteit-brussel]() ### AI overview Using imec's netzero modeling platform, researchers estimated embodied emissions for chiplet-based GPUs with doubled compute units and HBM capacity. The modeled 3D-scaled system increased embodied emissions by 89%, compared with 141% for 2.5D scaling, suggesting 3D integration can limit the emissions increase from GPU scaling. The excerpt does not specify the underlying model assumptions or other environmental impacts. ### Source excerpt Researchers at imec and Vrije Universiteit Brussels published "Embodied Emissions of 2.5D and 3D Scaling in Chipletized GPUs for Low-Carbon AI." Abstract "GPU compute resources are scaling to support growing AI workloads, leading to further rises in the climate change impact of hyperscale data centers that rely on high-performance GPUs. To model how packaging decisions... " read more The post 3D Integration Reduces Embodied-Emissions Impact Of GPU Scaling (imec, VUB) appeared first on Semiconductor Engineering. ## How Much Can Semiconductor Models Hide? DevFeed: [How Much Can Semiconductor Models Hide?]() Original publisher: [Read original article]() Author: Gregory Haley Published: 2026-10-28T07:01:04Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design](), [Data Quality]() Tags: [3d](), [3d-ic](), [about](), [account](), [added](), [advanced](), [advanced-packaging](), [ai](), [amkor](), [ansys](), [ase](), [brewer-science](), [but](), [can](), [chiplets](), [company](), [cross](), [digital-twins](), [eda](), [engineering](), [first](), [heterogeneous-integration](), [ip](), [make](), [manufacturing-packaging-and-materials](), [modeling](), [models](), [osats](), [packaging](), [pdf-solutions](), [prediction](), [processes](), [reduced-order-models](), [requires](), [silvaco](), [simulation](), [substrates](), [synopsys](), [thermal](), [top-stories]() ### AI overview Advanced packaging models must expose enough process behavior for other companies to predict how components work together while keeping recipes and formulations private. The article describes encrypted HFSS models as a way to use simulation models without revealing geometry or materials, and reduced-order or surrogate models as ways to make analysis practical; neither alone establishes that a model is valid for a given design. Surrogates are more reliable within their training region than outside it, while material properties can shift with temperature, curing, moisture, time, and interfaces. Useful handoffs therefore need to preserve relevant behavior and carry context such as data origin, calibration, assumptions, validity range, and intended decisions. The source emphasizes that model builders may still need detailed process recipes to create predictive models, even when users see only selected parameters. ### Source excerpt Advanced packaging requires models to cross company boundaries without exposing proprietary processes, but hiding too much can make the prediction break down. The post How Much Can Semiconductor Models Hide? appeared first on Semiconductor Engineering. ## Vibenix: Agentic Software Packaging and Maintenance with Nix DevFeed: [Vibenix: Agentic Software Packaging and Maintenance with Nix]() Original publisher: [Read original article]() Author: Martim Monis, Martin Schwaighofer, Nuno Saavedra, Alexandra Mendes, Rene Mayrhofer, Jo\\~ao F. Ferreira Published: 2026-10-28T04:00:00Z Content type: article Language: en Sources: [arXiv: Software Engineering]() Topics: [Nix](), [AI Agent](), [Agentic AI](), [agentic-coding](), [Build tool](), [Open Source]() Tags: [agentic](), [agentic-software](), [ai](), [ai-powered](), [arxiv](), [automatically](), [build](), [claude](), [claude-haiku-4-5](), [cs-se](), [dataset](), [dependencies](), [dependency](), [developers](), [distribution](), [environment](), [feedback](), [maintenance](), [nix](), [packaging](), [software]() ### AI overview Vibenix generates Nix packaging expressions through a rule-guided loop that builds recipes and repairs failures. On 466 NixBench tasks, it produced buildable packages in 95.3% of cases with Claude Haiku 4.5, versus 5.6% for a state-of-the-art single-shot LLM packaging tool. In manual review of 100 buildable packages, 47% were initially functionally correct; post-build refinement raised correctness by 35 percentage points. On the NixBench-Repair maintenance dataset, Vibenix succeeded on 87.6% of tasks. The results distinguish buildability from functional correctness and suggest iterative refinement can reduce the effort of creating and maintaining reproducible packages. ### Source excerpt arXiv:2610.24712v2 Announce Type: replace Abstract: Implicit dependencies, uncontrolled network access, and other build-environment impurities create intransparent software supply chains. Identifying every dependency affecting a build is a difficult task. Functional package management addresses this through reproducible packaging, ensuring software relies exclusively on declared, hermetically isolated inputs. However, creating build recipes remains complex and time-consuming, posing a significant barrier to adoption for developers and maintainers. We present Vibenix, an open-source AI-powered agent that bridges this gap by automatically generating Nix packaging expressions. Vibenix uses a large language model (LLM) to iteratively refine recipes through a rule-guided build-repair feedback loop. On 466 packaging tasks from our new NixBench dataset, Vibenix produced buildable packages in 95.3% of cases using Claude Haiku 4.5, compared with 5.6% for a state-of-the-art LLM-based single-shot packaging tool. Manual validation of 100 packages revealed that 47% of the buildable packages were initially functionally correct; a post-build refinement process based on the evaluator-optimizer pattern increased functional correctness by 35 percentage points. On our new NixBench-Repair dataset of package maintenance tasks, Vibenix achieved an 87.6% success rate. These results demonstrate how unreliable LLMs can generate rigorously defined, complete, auditable dependency trees for real-world software, reducing maintainer burden while providing a trustworthy foundation for secure software distribution. ## The AI Packaging Challenge: 5 Reasons Panels Are Gaining Momentum DevFeed: [The AI Packaging Challenge: 5 Reasons Panels Are Gaining Momentum]() Original publisher: [Read original article]() Author: Aaron Fellis, corporate vice president and general manager, Wet Equipment Technology Systems, Lam Research Published: 2026-10-26T13:00:00Z Content type: article Language: en Sources: [EE Times]() Topics: [Chip design](), [High-Performance Computing]() Tags: [accelerators](), [advanced-packaging](), [ai](), [ai-accelerators](), [ai-compute](), [ai-systems](), [ai-workloads](), [analog](), [analysis](), [architectures](), [bottlenecks](), [breakthrough](), [business](), [challenge](), [chip](), [collaboration](), [community](), [complex](), [designline](), [digital](), [education](), [ee-times](), [ee-times-university](), [eelife](), [eelive-electronic-design](), [eet](), [electrical-engineering](), [electronic-components](), [electronic-engineering-times](), [electronics](), [embedded-systems](), [fundamentals-courses](), [learning](), [limits](), [mixed-signal](), [news](), [opinion](), [packages](), [packaging](), [panel](), [part-search](), [processing](), [product-search](), [scale](), [semiconductors](), [software](), [sponsored-content](), [tech-papers](), [technology](), [video]() ### AI overview Panel-level packaging may help scale advanced AI packages as their size and complexity push against practical limits of round wafers. Square or rectangular panels can use processing area more efficiently for large packages, potentially improving scalability and production economics. The shift requires solving yield, process control, uniformity, automation, throughput, and standardization challenges, including achieving wafer-level precision across larger substrates. Progress also depends on collaboration to develop processes, qualify manufacturing flows, and build scalable production. The excerpt notes Lam Research's investments in panel-level R&D and manufacturing readiness, including its Salzburg Panel Center of Excellence; it presents panel processing as a developing path, not a completed transition. ### Source excerpt As AI pushes chip packages beyond traditional wafer limits, panel-level processing is emerging as a critical path to scale advanced packaging. The post The AI Packaging Challenge: 5 Reasons Panels Are Gaining Momentum appeared first on EE Times. ## Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec) DevFeed: [Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-10-26T07:02:36Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design]() Tags: [2-5d](), [3d](), [3d-integration](), [3d-stacking](), [advanced-packaging](), [ai-accelerators](), [architecture](), [capacity](), [cooling](), [dram](), [gpu](), [gpus](), [hbm](), [high-bandwidth-memory](), [hpc](), [imec](), [integration](), [memory](), [memory-bandwidth](), [organization](), [package](), [packaging](), [power-performance](), [semiconductor](), [simulations](), [stack](), [stacking](), [system-technology-co-optimization](), [technical-papers](), [thermal](), [thermal-management](), [vertical]() ### AI overview imec researchers evaluated a 3D GPU memory architecture that places DRAM dies vertically above the GPU, with cooling cavities between them, as an alternative to conventional 2.5D HBM and directly stacked HBM-on-GPU. Their package-level thermal simulations examined how stack height, memory capacity and organization, cavity materials, stack orientation, mold insertion, and an added memory-controller/network-on-chip tier affect the thermal design envelope. The excerpt does not report simulation results. ### Source excerpt Researchers at imec published "Beyond HBM-on-GPU: Thermal Design Envelope for 3D Volumetric DRAM-on-GPU Integration." Summary: Researchers evaluated a 3D memory architecture that rotates DRAM dies vertically above a GPU and places cooling cavities between them as an alternative to conventional 2.5D HBM and direct-stacked HBM-on-GPU. Package-level thermal simulations examined stack height, memory capacity and organization,... " read more The post Vertical DRAM Stacking Expands Thermal Design Space Beyond HBM-on-GPU (imec) appeared first on Semiconductor Engineering. ## Chip Scaling Moves Beyond The Transistor DevFeed: [Chip Scaling Moves Beyond The Transistor]() Original publisher: [Read original article]() Author: Gregory Haley Published: 2026-10-22T07:05:16Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design](), [Electrical engineering and computer science (EECS)]() Tags: [2](), [2023](), [2026](), [3](), [advanced](), [advanced-packaging](), [advantest](), [agentic-ai](), [ai](), [amkor](), [ase](), [chip](), [chiplets](), [co-packaged-optics](), [conversations](), [cpo](), [digital-twins](), [engineering](), [ev-group](), [hbm](), [heterogeneous-integration](), [imec](), [inspection](), [intel](), [intel-foundry](), [known-good-assembly](), [known-good-die](), [lam-research](), [manufacturing-packaging-and-materials](), [marvell](), [metrology](), [microtronic](), [optical-interconnects](), [packaging](), [photonics](), [power-delivery](), [scaling](), [semi](), [semicon](), [semicon-west](), [semicon-west-2026](), [semiconductor](), [semiconductor-engineering](), [semiconductor-manufacturing](), [semiconductor-test](), [silicon-photonics](), [test](), [top-stories](), [transistor]() ### AI overview Semiconductor scaling is becoming a system-level challenge: performance and manufacturability depend on coordinating silicon, packaging, memory, interconnects, power, cooling, test, and software. The article describes advanced packaging as part of system architecture, while larger heterogeneous assemblies raise yield, reliability, cost, inspection, and traceability demands. Photonics moving closer to compute adds alignment, metrology, and optical test requirements that must reach semiconductor manufacturing throughput; some assembly processes are difficult to rework. AI is already used in design and manufacturing, and agentic systems can explore parameter spaces too large for manual search, but letting them change recipes or make production decisions raises questions about human approval and evidence. The industry's task is to combine these technologies repeatedly, reliably, and economically at volume. ### Source excerpt SEMICON West 2026: Advanced packaging, photonics, test, and AI are increasingly intertwined; very different conversations ahead. The post Chip Scaling Moves Beyond The Transistor appeared first on Semiconductor Engineering. ## What Breaks When Packaging Moves From Wafer To Panel? DevFeed: [What Breaks When Packaging Moves From Wafer To Panel?]() Original publisher: [Read original article]() Author: Gregory Haley Published: 2026-10-22T07:01:11Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design]() Tags: [advanced-packaging](), [ai](), [amkor](), [applied-materials](), [ase](), [brewer-science](), [critical-manufacturing](), [fraunhofer-izm](), [glass-substrates](), [hpc](), [intel-foundry](), [interposers](), [manufacturing-packaging-and-materials](), [packaging](), [panel](), [panel-level-packaging](), [process-control](), [rdl](), [special-reports](), [synopsys]() ### AI overview Panel packaging can fit more large packages per process cycle than a round wafer, but its area advantage depends on manufacturing control and yield. In one ASE comparison, output rises from 9 units on a 300mm wafer to 16 on a 300mm panel and 72 on an intact 600mm panel; dividing the large panel into four 300mm pieces yields 64 and lowers assembly risk because equipment for intact 600mm processing is not yet fully available. Panel flows also require changes such as slot-die resist coating and direct imaging, while demanding uniformity, overlay, and handling across larger surfaces. Thermal and mechanical history can shift dies, warp panels, or damage glass; glass improved dimensional stability in cited tests but can still experience nonlinear die shift. Rework, early inspection, metrology, and simulation help manage the risk that defects discovered late will erase the savings from higher utilization. The article suggests different steps may favor different panel sizes, with yield and equipment readiness constraining the economically useful format. ### Source excerpt Engineers are discovering many things they thought were process assumptions were actually wafer assumptions. The post What Breaks When Packaging Moves From Wafer To Panel? appeared first on Semiconductor Engineering. ## Foundries And OSATs Increasingly Overlap DevFeed: [Foundries And OSATs Increasingly Overlap]() Original publisher: [Read original article]() Author: Bryon Moyer Published: 2026-10-22T07:01:03Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Chip design](), [Finance](), [tsmc](), [High-Performance Computing]() Tags: [2-5d](), [2-5d-integration](), [2025](), [2026](), [3d](), [added](), [adoption](), [advanced](), [advanced-packaging](), [ai](), [alignment](), [all](), [amkor](), [ase-group](), [brewer-science](), [capacity](), [engineering](), [ev-group](), [first](), [foundry](), [growth](), [hybrid-bonding](), [intel-foundry](), [manufacturing-packaging-and-materials](), [mitsubishi-chemical](), [osat](), [osats](), [overlap](), [packaging](), [panel](), [semiconductor](), [silvaco](), [top-stories](), [zeiss]() ### AI overview Advanced packaging growth and foundry capacity constraints are shifting some backend work toward OSATs, blurring the traditional division between wafer fabrication and assembly. OSATs are adding capabilities for 2.5D integration and panel packaging, while foundries prioritize newer-node fabrication and may offload legacy or overflow work. This shift brings wafer-fab-style lithography and materials into packaging as finer-pitch redistribution layers demand more precise patterning and alignment. Foundries still dominate high-volume hybrid bonding; OSAT adoption may grow if demand exceeds foundry capacity and processes mature. OSATs must invest in new equipment, with returns depending on utilization and customer commitments. Their spillover role also leaves them more exposed to changing demand, according to the source. ### Source excerpt Advanced packaging growth and capacity constraints are pushing more onto OSATs. The post Foundries And OSATs Increasingly Overlap appeared first on Semiconductor Engineering. ## Linux Won the Server Market. Why Is Its Desktop Still a Gamble? DevFeed: [Linux Won the Server Market. Why Is Its Desktop Still a Gamble?]() Original publisher: [Read original article]() Author: David Timothy Published: 2026-10-20T20:47:21Z Content type: opinion Language: en Sources: [HackerNoon]() Topics: [Linux](), [Linux Kernel](), [Flatpak](), [snap](), [AppImage](), [Firefox](), [Pipewire](), [pacman]() Tags: [adoption](), [desktop](), [hackernoon-top-story](), [hardware](), [hardware-video-acceleration](), [integration](), [linux](), [linux-desktop](), [linux-fractional-scaling](), [linux-power-management](), [linux-suspend-issues](), [linux-vs-windows](), [operating-systems](), [packaging](), [support](), [technology](), [updates](), [windows]() ### AI overview Linux has capable desktop components, but users still face inconsistent integration across hardware, applications, packaging, and updates. The article traces concrete pain points: fractional scaling and screen sharing depend on coordinated compositor, toolkit, portal, and app support; suspend reliability varies with firmware and drivers; video decoding depends on codec, browser, driver, and sandbox compatibility; and package formats and GNOME extensions can complicate updates or disrupt workflows. It argues the core weakness is fragmented product ownership rather than missing technology. Proposed remedies include publishing supported hardware configurations, testing complete user journeys on physical machines, defining compatibility contracts, and funding teams to own cross-project failures. The article qualifies that these issues are configuration dependent, acknowledges progress and constraints, and avoids claiming Linux always fails or that Windows is flawless. ### Source excerpt Linux has the technology to challenge Windows, but inconsistent desktop integration, hardware support, packaging, and updates still hold it back. ## A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame) DevFeed: [A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-10-18T22:51:32Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Finite Element Method (FEM)](), [Chip design]() Tags: [2-5d](), [3d](), [3d-ic](), [advanced-packaging](), [ai](), [ai-ml-dl](), [cadence](), [chiplet](), [chiplets](), [coupling](), [design-verification](), [domain-decomposition](), [engineering](), [flux](), [heat-flux](), [iteration](), [modeling](), [models](), [notre-dame](), [operator-learning](), [packaging](), [semiconductor](), [semiconductor-engineering](), [simulation](), [technical-papers](), [thermal-analysis](), [thermal-modeling](), [thermal-simulation](), [topology](), [university-of-notre-dame]() ### AI overview Researchers from Cadence Design Systems and the University of Notre Dame propose DAIST, a composable AI-accelerated solver for thermal analysis of heterogeneous 2.5D and 3D IC packages. It divides package simulations into block-level subdomains, uses neural operators for those subdomains, and couples them through iterative exchanges of temperature and heat flux. The paper reports reuse across unseen package topologies and speedups of up to 178x, with reported mean temperature errors of 0.068% and 0.323% on two evaluated systems. ### Source excerpt Researchers at Cadence Design Systems and the University of Notre Dame published "A Composable AI-Accelerated Iterative Solver for 3D-IC Thermal Modeling." Abstract: "Accurate thermal analysis of heterogeneous 2.5D/3D-IC packages is essential yet computationally prohibitive. A single full-package FEM simulation can take hours, while AI-based surrogates treat the entire stack as a monolithic prediction target and... " read more The post A Composable Thermal Solver For Heterogeneous 2.5D/3D-IC Packages (Cadence, Notre Dame) appeared first on Semiconductor Engineering. ## Monolithic 3D Memristor-TFT Stack For Programmable Neuromorphic Computing (SNU, Yonsei) DevFeed: [Monolithic 3D Memristor-TFT Stack For Programmable Neuromorphic Computing (SNU, Yonsei)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-10-06T21:29:31Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Computing](), [stream-processing](), [Sustainable Computing]() Tags: [3d-ic](), [ai-ml-dl](), [architectures](), [back-end-of-line](), [beol](), [computing](), [emerging-memory](), [hfo2](), [in2o3](), [memory](), [memristors](), [monolithic-3d-integration](), [neuromorphic](), [neuromorphic-computing](), [packaging](), [reservoir-computing](), [resistive-memory](), [seoul-national-university](), [technical-papers](), [temporal](), [temporal-computing](), [tft](), [thin-film-transistors](), [transistors](), [yonsei-university]() ### AI overview Researchers at Seoul National University and Yonsei University report a monolithically integrated memristor-thin-film transistor reservoir kernel. The abstract says it enables electrically programmable temporal dynamics across a wide timescale, addressing limits in hardware reservoirs whose dynamics are fixed or narrowly tunable. ### Source excerpt Researchers at Seoul National University and Yonsei University published a technical paper titled "Monolithic three-dimensionally integrated memristor-thin-film transistor for electrically programmable multimode reservoir computing." Abstract Excerpt: "Reservoir computing offers an efficient framework for processing temporal information, but most hardware reservoirs exhibit fixed or narrowly tunable dynamics determined by intrinsic material relaxation time. A monolithically integrated... " read more The post Monolithic 3D Memristor-TFT Stack For Programmable Neuromorphic Computing (SNU, Yonsei) appeared first on Semiconductor Engineering. ## Python 3.15 Gets a Surprise RC3 and Other Python News for October 2026 DevFeed: [Python 3.15 Gets a Surprise RC3 and Other Python News for October 2026]() Original publisher: [Read original article]() Author: Bartosz Zaczyński Published: 2026-10-05T14:00:00Z Content type: news Language: en Sources: [Real Python]() Topics: [Python](), [SQLAlchemy](), [Wagtail]() Tags: [ai-apis](), [packaging]() ### AI overview The October Python roundup reports that lazy-import bugs prompted Python 3.15 RC3 and delayed the final release to October 9. It covers the first Python Packaging Council, revised PyPI download counting, Polars 2.0 release candidates, SQLAlchemy 2.1 compatibility changes, and breaking AI API changes. Practical guidance includes testing encoding assumptions, checking dependency requirements, and isolating autonomous coding agents. ### Source excerpt Python 3.15 gets a surprise RC3, the first Packaging Council is elected, Polars 2.0 and SQLAlchemy 2.1 arrive, and AI APIs break Python code again. ## A Bootiful Podcast: JReleaser creator and fellow Java Champion Andres Almiray DevFeed: [A Bootiful Podcast: JReleaser creator and fellow Java Champion Andres Almiray]() Original publisher: [Read original article]() Author: joshlong Published: 2026-10-01T00:00:00Z Content type: article Language: en Sources: [Spring]() Topics: [Java](), [JavaFX](), [CI/CD]() Tags: [automate](), [batch](), [boot](), [checksums](), [cloud](), [dependencies](), [desktop](), [distribution](), [electron](), [event-driven](), [future](), [generate](), [github](), [gitlab](), [java](), [javafx](), [jvm](), [maven-central](), [microservices](), [native](), [package](), [packaging](), [podcast](), [reactive](), [releases](), [serverless](), [shipping](), [spring](), [web-applications]() ### AI overview JReleaser helps Java projects automate releases across services such as GitHub, GitLab, and Maven Central, and can create native installers and distribution bundles, compute signatures and checksums, and post announcements. The excerpt says the conversation also covers its use for desktop applications and command-line tools, including how it relates to JLink and JPackage. It provides no detailed comparisons or step-by-step guidance. ### Source excerpt Hi, Spring fans! What if the JVM could feel as frictionless as the modern dev tools people rave about on other platforms? In this wide-ranging, high-energy conversation, you'll hear two longtime friends (Andres Almiray is a fellow Java champion and a legend) geek out over the future of desktop Java, the pain of Electron, the elegance of JavaFX, and the tools making it all easier to ship. The discussion dives into a brand-new favorite workflow for managing environments and dependencies, then pivots into the powerhouse that is JReleaser -- the tool that helps Java projects publish releases, package native installers, generate distribution bundles, compute signatures and checksums, post announcements to social platforms, and even automate releases across GitHub, GitLab, Maven Central, and more. Along the way, they explore how JReleaser powers everything from desktop apps to command-line tools, how it fits with JLink and JPackage, why it's become essential for projects like JBang and more, and how it's helping make Java distribution feel modern again. If you care about shipping software cleanly, packaging it beautifully, or just want to hear passionate builders talk about making developer life better, this one is packed with insight, nostalgia, and a lot of "wait, it does that too?" moments. ## Designing Multi-kW Power Delivery In 3D Heterogeneously Integrated Systems (U. of Minnesota) DevFeed: [Designing Multi-kW Power Delivery In 3D Heterogeneously Integrated Systems (U. of Minnesota)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-22T17:09:41Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [3D](), [systems]() Tags: [2-5d-integration](), [2026](), [3d](), [3d-ic](), [advanced-packaging](), [architectures](), [chiplets](), [design-verification](), [designing](), [distributed](), [engineering](), [heterogeneous-integration](), [packaging](), [pdn](), [performance](), [power-delivery](), [power-distribution-networks](), [power-integrity](), [power-management](), [power-performance](), [reliability](), [semiconductor](), [systems](), [technical-papers](), [university](), [university-of-minnesota](), [voltage-regulators]() ### AI overview This article reports on a University of Minnesota technical paper about methodologies for delivering multiple kilowatts of power to advanced 3D heterogeneous chiplet systems. The work addresses high power densities and pin-count bottlenecks using distributed power delivery systems optimized for performance and reliability while meeting thermal and other system constraints. ### Source excerpt Researchers at the University of Minnesota published a technical paper titled "Toward Multi-kW Power Delivery Methodologies for Advanced 3D Heterogeneous Integration." Abstract Excerpt: "Computationally powerful systems require significant power for computation: reliable and robust power delivery is a major challenge in light of high power densities and pin count bottlenecks. This paper overviews approaches to... " read more The post Designing Multi-kW Power Delivery In 3D Heterogeneously Integrated Systems (U. of Minnesota) appeared first on Semiconductor Engineering. ## Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech) DevFeed: [Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:37:45Z Content type: news Language: en Sources: [Semiconductor Engineering]() Topics: [Benchmark](), [Artificial Intelligence](), [3D]() Tags: [2-5d-ic](), [3d](), [3d-ic](), [advanced-packaging](), [ai](), [ai-for-eda](), [ai-ml-dl](), [benchmark](), [chiplets](), [design-verification](), [engineering](), [ic-thermbench](), [machine-learning](), [ood](), [out-of-distribution-generalization](), [packaging](), [paper](), [power-performance](), [semiconductor](), [shanghaitech-university](), [technical-papers](), [technical-university-of-munich](), [thermal-management](), [thermal-modeling](), [thermal-prediction](), [thermal-simulation](), [university-of-technology-sydney]() ### AI overview Researchers from the University of Technology Sydney, ShanghaiTech University, and Technical University of Munich published IC-ThermBench, an open benchmark for evaluating generalizable AI models for thermal behavior in 2.5D and 3D integrated circuits. The benchmark includes steady-state, transient, industrial package, and 2.5D chiplet tasks, including a 50,000-sample extension. ### Source excerpt Researchers at the University of Technology Sydney, ShanghaiTech University, and Technical University of Munich published a technical paper titled "IC-ThermBench: An Open, Progressive Benchmark for Generalizable 2.5D/3D-IC Thermal Learning." Abstract Excerpt: "We introduce IC-ThermBench, an open and progressive benchmark that combines established 3D-IC steady-state, transient, and industrial package tasks with a new 50,000-sample 2.5D chiplet... " read more The post Open Benchmark Evaluates AI Thermal Models for 2.5D and 3D ICs (UTS, TU Munich, ShanghaiTech) appeared first on Semiconductor Engineering. ## Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University) DevFeed: [Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University)]() Original publisher: [Read original article]() Author: Technical Paper Link Published: 2026-09-19T18:23:56Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Computing](), [Scalability](), [systems](), [Network]() Tags: [2026](), [2d-mesh](), [ai-ml-dl](), [analog](), [architecture](), [architectures](), [arq](), [automatic-repeat-request](), [brainscales](), [brainscales-2](), [chiplet-interconnects](), [chiplets](), [computing](), [cost](), [credit-based-flow-control](), [data](), [data-movement](), [die-to-die-communication](), [engineering](), [error-control](), [flexibility](), [heidelberg-university](), [implementing](), [mixed-signal-circuits](), [network](), [neuromorphic](), [neuromorphic-computing](), [packaging](), [paper](), [routing-chiplets](), [scaling](), [semiconductor](), [snn](), [spiking-neural-networks](), [system](), [systems](), [technical-papers]() ### AI overview Researchers at Heidelberg University describe a unified interconnection network for scaling the BrainScaleS-2 neuromorphic system with chiplet-based designs. The proposed routing chiplet connects multiple units in a 2D mesh and handles both error-tolerant spike traffic and error-intolerant configuration and processing-unit data. ### Source excerpt Researchers at Heidelberg University published a technical paper titled "A Unified Interconnection Network for Chiplet-Based Scaling of the BrainScaleS Neuromorphic System." Abstract Excerpt: "To overcome the challenges of scaling analog designs, chiplet-based designs offer a promising approach with cost and flexibility advantages over monolithic scaling. Implementing a chiplet-based BSS-2* architecture requires an interconnection network that... " read more The post Unified Chiplet Network Scales Neuromorphic Computing Systems (Heidelberg University) appeared first on Semiconductor Engineering. ## How to Sell Digital Downloads: Delivery Mechanics DevFeed: [How to Sell Digital Downloads: Delivery Mechanics]() Original publisher: [Read original article]() Author: Deepak Jangir Published: 2026-09-19T00:00:00Z Content type: tutorial Language: en Sources: [Dodo Payments Blog]() Topics: [Automation](), [Digital Trust](), [online-fraud-prevention]() Tags: [1-5](), [2](), [3](), [about](), [account](), [delivery](), [digital](), [digital-products](), [downloads](), [failed](), [files](), [guide](), [how-to](), [keys](), [license](), [license-keys](), [links](), [operational](), [packaging](), [payments](), [refunds](), [vat]() ### AI overview Reliable digital-download fulfilment depends on packaging files clearly, serving them from private storage through short-lived links, and letting buyers regenerate links through a self-service portal. The guide recommends creating entitlements and issuing downloads or license keys only after server-confirmed payment events; verify webhook signatures and make handlers idempotent. Static files can be copied once downloaded, so link expiry, download caps, watermarking, and clear licensing deter casual sharing but cannot prevent copying. Software can pair hosted installers with keys that support activation, validation, and revocation. Sellers must account for buyer-location tax rules, either by registering and filing themselves or using a merchant of record. Since digital goods cannot be returned, publish a clear refund policy and revoke access where possible. For failed deliveries, support repeat downloads, self-service retrieval, and order-level logs to quickly diagnose missing entitlements. ### Source excerpt The operational guide to selling digital downloads: packaging files, expiring links, license keys, VAT on digital goods, refunds, and failed-delivery recovery. ## AI's Storage Problem Is a Packaging Problem DevFeed: [AI's Storage Problem Is a Packaging Problem]() Original publisher: [Read original article]() Author: Chiung Lee Published: 2026-09-17T07:05:40Z Content type: article Language: en Sources: [Semiconductor Engineering]() Topics: [Artificial Intelligence](), [cloud-infrastructure](), [data centers](), [data]() Tags: [3d-nand](), [advanced-packaging](), [ai](), [ai-models](), [amkor](), [blogs-md](), [chip-package-system](), [engineering](), [hybrid-bonding](), [inference](), [infrastructure](), [manufacturing-packaging-and-materials](), [nand](), [osats](), [packaging](), [semiconductor](), [ssds](), [storage]() ### AI overview The article argues that AI-driven data growth is making storage infrastructure a central system constraint. It examines how thinner dies, taller memory stacks, hybrid bonding, NAND flash, DRAM, HBM, and advanced packaging are being used to support expanding AI, data-center, device, and automotive workloads. ### Source excerpt How thinner dies, taller stacks, and hybrid bonding are carrying NAND into the AI era. The post AI's Storage Problem Is a Packaging Problem appeared first on Semiconductor Engineering. ## Seven years of bitwise: a weekend project, a Hackernews front page, and the long road into Debian DevFeed: [Seven years of bitwise: a weekend project, a Hackernews front page, and the long road into Debian]() Original publisher: [Read original article]() Author: Ramon Published: 2026-09-11T15:21:24Z Content type: article Language: en Sources: [Ramon Fried]() Topics: [experience report](), [project release](), [Test-driven development]() Tags: [alpine](), [ascii](), [aur](), [autotools](), [bits](), [c](), [calculator](), [debian](), [distributions](), [fedora](), [freebsd](), [hacker-news](), [hackernews](), [history](), [homebrew](), [kde](), [keys](), [linux](), [low-level](), [ncurses](), [nix](), [open-source](), [packaging](), [project](), [software](), [vim]() ### AI overview bitwise began as a terminal alternative to opening KDE Calculator for inspecting register bits; the author says writing the program was easier than getting it packaged and distributed. Early additions included Vim movement keys for navigating the binary display and a plain command-line mode, which most users now use. During ten weeks without feedback, the author added an expression parser, unit tests, history, last-result reuse, ASCII output, and a distinction between KiB and kB. A second Hacker News post reached the front page with 113 points after its title shifted from describing the program to describing what it did for users. The excerpt says bitwise later reached many distributions and package systems, but ends before explaining that experience further. ### Source excerpt I started bitwise because I was tired of opening the KDE calculator. Seven years, one Hacker News front page and sixteen distributions later, here's what I learned -- mostly about how hard it is to get software to people. ## Built for agents: Omarchy's pipeline moves to DigitalOcean DevFeed: [Built for agents: Omarchy's pipeline moves to DigitalOcean]() Original publisher: [Read original article]() Author: Paddy Srinivasan Published: 2026-09-09T15:30:15Z Content type: news Language: en Sources: [DigitalOcean]() Topics: [AI Infrastructure](), [CI/CD](), [self-service](), [Software Testing]() Tags: [agent](), [agentic](), [agents](), [build](), [digitalocean](), [inference](), [infrastructure](), [linux](), [marketplace](), [news](), [nonprofit](), [omarchy](), [open-source](), [packaging](), [parallel](), [pipeline](), [pr-reviews](), [production](), [qa](), [qa-testing](), [release]() ### AI overview Omarchy has moved its packaging builds, PR review agents, and QA testing to DigitalOcean. The pipeline runs bursty, parallel jobs: a single `doctl` command can provision a Droplet, run a job, call separately configured inference services, then destroy the Droplet. DigitalOcean is also joining the Omacom Foundation as a Founding Corporate Patron and will provide agentic compute. A one-click Omarchy Droplet on the DigitalOcean Marketplace is planned, but has not yet been released. ### Source excerpt Omarchy is a keyboard-first Linux desktop built on Arch and Hyprland by David Heinemeier Hansson (DHH), and its production pipeline, packaging builds, PR review agents, and QA testing, now run on DigitalOcean. Agent workloads don't behave like a typical web server. They're bursty and parallel: an agent spins up, does one job, and shuts down. Omarchy's pipeline is a real example of that pattern, and DigitalOcean infrastructure complements its needs. A single doctl command can provision a Droplet, run the job, call separately configured inference services, and destroy the Droplet when the work is done. Alongside the infrastructure move, DigitalOcean is joining the Omacom Foundation, the nonprofit that funds Omarchy's infrastructure and the open source projects it depends on, as a Founding Corporate Patron, and will serve as Omarchy's agentic compute provider. "I'm thrilled to have DigitalOcean become a Founding Corporate Patron of the Omacom Foundation, and our new agentic compute provider as well. We have such grand ambitions for Omarchy, and it's time we upgrade our technical infrastructure to match. Whether it's build servers for packaging, agent runners for PR reviews, or Droplets for QA testing, DigitalOcean simply has everything we need. They also have the right mindset for the future and our new age of agents. Couldn't imagine a better fit!" -- David Heinemeier Hansson, creator of Omarchy What's Next Coming soon, DigitalOcean and Omarchy plan to release a 1-click Omarchy Droplet available through the DigitalOcean Marketplace, enabling developers to quickly deploy the same environment used by the maintainers. ## Our endorsements for Python's first Packaging Council DevFeed: [Our endorsements for Python's first Packaging Council]() Original publisher: [Read original article]() Author: hey@astral.sh (The Astral team) Published: 2026-09-04T00:00:00Z Content type: opinion Language: en Sources: [Astral]() Topics: [Python](), [PyPI]() Tags: [astral](), [governance](), [packaging]() ### AI overview Astral endorses William Woodruff, Pradyun Gedam, Ralf Gommers, and Donald Stufft for the inaugural Python Packaging Council. It argues that their experience in packaging standards, security, infrastructure, scientific computing, and governance can help the council improve Python packaging and its decision-making processes. ### Source excerpt Astral is proud to endorse William Woodruff, Pradyun Gedam, Ralf Gommers, and Donald Stufft for the inaugural Python Packaging Council. [Next page]()