# Processor Published articles for Processor. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Libreboot 20140309 release DevFeed: [Libreboot 20140309 release]() Original publisher: [Read original article]() Author: Leah Rowe Published: 2026-09-17T04:32:50.666044Z Content type: release Language: en Sources: [News about Libreboot releases and development]() Topics: [libreboot](), [boot]() Tags: [article](), [battery](), [bios](), [boot](), [canoeboot](), [coreboot](), [crypto](), [debugging](), [free-software](), [libre](), [libreboot](), [opensource](), [processor](), [release](), [uefi]() ### AI overview The Libreboot 20140309 release reduces boot time, adds cryptographic and cryptodisk modules to GRUB, includes cbfstool in binary archives, and provides separate ROM images for faster booting or debugging. It also describes changes intended to reduce battery impact. ### Source excerpt Article: Libreboot 20140309 release Web link: https://libreboot.org/news/libreboot20140309.html ## Sound Open Firmware 2.15 Released With AMD ACP 7.x Support, Intel UAOL DevFeed: [Sound Open Firmware 2.15 Released With AMD ACP 7.x Support, Intel UAOL]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-09-15T13:04:40Z Content type: release Language: en Sources: [Phoronix]() Topics: [Embedded Software Dev](), [Open Source](), [intel](), [Security](), [qemu](), [Xtensa](), [Fuzzing/Fuzz testing](), [POSIX](), [Testing]() Tags: [desktop-linux](), [driver](), [dsp](), [firmware](), [fuzzing](), [intel](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [posix](), [processor](), [qemu](), [security](), [testing](), [ubuntu-benchmarks](), [ubuntu-hardware](), [usb](), [xtensa]() ### AI overview Sound Open Firmware 2.15 adds user-space, memory-protected module execution, AMD ACP 7.x and NXP i.MX8MP support, Intel UAOL USB audio offload, testing targets, security hardening, and new audio processing modules. ### Source excerpt Sound Open Firmware as the open-source, vendor-independent audio DSP firmware stack and driver framework is out today with a new feature update... ## Amlogic A123X and C305X2 Arm Cortex-A320 SoCs target industrial and low-power AIoT applications DevFeed: [Amlogic A123X and C305X2 Arm Cortex-A320 SoCs target industrial and low-power AIoT applications]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-11T03:13:41Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Arm](), [cpu](), [Embedded Systems](), [Artificial Intelligence](), [Internet of things](), [Hardware](), [object-detection](), [Neural Network](), [Transformer]() Tags: [aiot](), [amlogic](), [arm](), [armv9](), [camera](), [computer-vision](), [cortex-a320](), [edge-ai](), [embedded](), [ethernet](), [h-264](), [hardware](), [iot](), [linux](), [llm](), [low-power](), [neural](), [npu](), [object-detection](), [processor](), [security](), [soc]() ### AI overview Amlogic has announced the A123X quad-core and C305X2 dual-core Arm Cortex-A320 SoCs for industrial and battery-powered edge AI and IoT devices. The preliminary specifications include video encoding and decoding, NPUs, image signal processing, camera interfaces, networking, USB, and low-power features. The article notes that full specifications, block diagrams, and software details are not yet available. ### Source excerpt Amlogic has unveiled the A123X quad-core and C305X2 dual-core Arm Cortex-A320 SoCs for industrial and battery-powered Edge AI and IoT applications such as robots, dashcams, IP cameras, video conferencing equipment, and so on. The Arm Cortex-A320 low-power Armv9 CPU core was introduced in February 2025, and Amlogic is the first silicon vendor to announce Cortex-A320 SoCs. Details are sparse, with no full specifications or block diagrams and limited software information, but let's see what we know so far. Amlogic A123X Amlogic A123X specifications: CPU - Quad-core Arm Cortex-A320 processor (Armv9.2-A, SVE2) GPU - None or not disclosed VPU H.264/H.265 encoding at 4K @ 60fps H.264/H.265 decoding at 4K @ 30fps AI 4 TOPS ADLA2 NPU for object detection and tracking CNN models 8 TOPS ADLA3 NPU supporting hardware-accelerated Transformer operations for ViT, LLM, etc. Neural network-based hardware SED engine for low-power audio event identification ISP - Low-light HDR ISP Supports [...] The post Amlogic A123X and C305X2 Arm Cortex-A320 SoCs target industrial and low-power AIoT applications appeared first on CNX Software - Embedded Systems News. ## Why is the x86 undefined instruction called ud2? Why 2? DevFeed: [Why is the x86 undefined instruction called ud2? Why 2?]() Original publisher: [Read original article]() Author: Raymond Chen Published: 2026-09-10T14:00:00Z Content type: article Language: en Sources: [Raymond Chen]() Topics: [x86](), [Assembly](), [Compiler](), [Exception](), [intel]() Tags: [compiler](), [exception](), [intel](), [old-new-thing](), [other](), [processor](), [x86]() ### AI overview The article explains why the x86 undefined instruction is called ud2. It describes how software used byte sequences that reliably raised an invalid opcode exception, how Intel later provided a standardized instruction, and how compiler output can use it to mark unreachable code and cause a deliberate crash. ### Source excerpt It came after ud0 and ud1. The post Why is the x86 undefined instruction called ud2? Why 2? appeared first on The Old New Thing. ## Qualcomm introduces Dragonwing Q-2390 and IQ-2390 for consumer and industrial AIoT applications DevFeed: [Qualcomm introduces Dragonwing Q-2390 and IQ-2390 for consumer and industrial AIoT applications]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-01T14:24:27Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Embedded Systems](), [cpu](), [Arm](), [RISC-V](), [GPU]() Tags: [4g-lte](), [android](), [artificial-intelligence-ai](), [camera](), [cortex-a55](), [cortex-a78](), [dsp](), [embedded](), [embedded-systems](), [hardware](), [hexagon](), [industrial](), [iot](), [linux](), [npu](), [processor](), [products](), [qualcomm](), [qualcomm-dragonwing](), [risc-v](), [ubuntu](), [wifi-5](), [yocto](), [zephyr](), [zephyr-os]() ### AI overview Qualcomm announced the Dragonwing Q-2390 and IQ-2390 quad-core Cortex-A78/A55 processors for consumer, commercial, and industrial AIoT applications. The Q-2390 targets devices such as retail and smart home products, while the IQ-2390 targets industrial automation, machine vision, building management, and energy systems. The processors include optional RISC-V real-time cores, Adreno graphics, Hexagon processing, camera and display interfaces, networking, and support for Android, Yocto Linux, Ubuntu, and Zephyr RTOS. ### Source excerpt Qualcomm has announced the Qualcomm Dragonwing Q-2390 and IQ-2390 quad-core Cortex-A78/A55 processors for AIoT consumer, commercial and industrial applications. The Dragonwing Q-2390 processor is designed for commercial and consumer devices, notably for applications such as retail and smart home products, as well as smart displays and enterprise edge devices, while the Dragonwing IQ-2390 processor is the SKU from the Dragonwing IQ2 Series designed for industrial automation, machine vision, building management and energy systems. Qualcomm IQ-2390 and Q-2390 specifications: CPU 1x Arm Cortex-A78 core up to 1.5 or 1.9 GHz depending on SKU 3x Arm Cortex-A55 cores up to 1.5 or 1.9 GHz depending on SKU Optional SiFive E61 RISC-V real-time core up to 600MHz with 768kB memory Cache - 512 KB L3 cache GPU - Qualcomm Adreno 704 up to 1.1 GHz Audio DSP - Qualcomm Hexagon V66 up to 1.1 GHz NPU - Qualcomm Hexagon up to 1.1 TOPS DPU [...] The post Qualcomm introduces Dragonwing Q-2390 and IQ-2390 for consumer and industrial AIoT applications appeared first on CNX Software - Embedded Systems News. ## IBM Quantum Nighthawk r2--more circuits, faster DevFeed: [IBM Quantum Nighthawk r2--more circuits, faster]() Original publisher: [Read original article]() Published: 2026-08-31T14:30:00Z Content type: article Language: en Sources: [IBM Research]() Topics: [ibm](), [Quantum Computing](), [Hardware]() Tags: [hardware](), [ibm](), [performance](), [processor](), [quantum](), [quantum-computing](), [quantum-error-correction-mitigation](), [quantum-systems](), [release](), [speed]() ### AI overview IBM Quantum Nighthawk r2 uses independent high-speed qubit reset to execute more than 100,000 circuits per second, providing up to 25 times the circuit throughput of IBM Quantum Heron. The 120-qubit processor also supports accurate results on circuits with more than 7,500 gates. ### Source excerpt High-speed, independent qubit reset boosts circuit throughput 25x over Heron while enabling accurate observable estimation on circuits with 7,500+ gates. ## Hot Chips 2026: Fujitsu's Monaka CPU DevFeed: [Hot Chips 2026: Fujitsu's Monaka CPU]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-26T01:20:30Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [cpu](), [Arm](), [Algorithm](), [intel]() Tags: [2026](), [algorithm](), [amd](), [arm](), [cpu](), [fujitsu](), [hpc](), [intel](), [processor]() ### AI overview The article examines Fujitsu's Monaka CPU, which is intended to improve on A64FX's limitations for general-purpose workloads while retaining strong HPC vector throughput. It discusses Monaka's three-level TAGE branch predictor and contrasts it with A64FX's perceptron-like predictor. ### Source excerpt Building on a long history of HPC-focused cores, and looking beyond HPC ## Hot Chips 2026: Intel's Diamond Rapids DevFeed: [Hot Chips 2026: Intel's Diamond Rapids]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-25T06:20:03Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [cpu](), [intel](), [Cache](), [IO](), [x86]() Tags: [2026](), [cache](), [cpu](), [intel](), [io](), [processor](), [x86]() ### AI overview The article examines Intel's Diamond Rapids server CPU, including its 3D-stacked L3 cache, die and packaging design, revised 256-core specification, 1.6 TB/s memory bandwidth, 128 PCIe Gen 6 lanes, and two new x86 ISA extensions. It compares these characteristics with AMD's Venice processor. ### Source excerpt Hello you fine Internet folks, ## How fast is C++26's std::hive? DevFeed: [How fast is C++26's std::hive?]() Original publisher: [Read original article]() Author: Daniel Lemire Published: 2026-08-02T17:00:10Z Content type: article Language: en Sources: [Daniel Lemire]() Topics: [container](), [Data structures](), [cpu](), [intel]() Tags: [compiler](), [container](), [data-structure](), [intel](), [processor](), [standard-library]() ### AI overview The article benchmarks a C++26 std::hive implementation against vector, list, and another container. In the reported tests, hive insertion costs about twice as much as vector insertion, while iteration is about eight times slower than vector and no faster than linked-list iteration. ### Source excerpt C++26 adds a new container to the standard library: std::hive. It is meant to occupy the ground between std::vector and std::list. Like a vector, it keeps its elements in contiguous blocks of memory, so scanning it does not require you to chase a pointer for every element. Like a list, it never moves an element ... Continue reading How fast is C++26's std::hive? ## Intel Reportedly Provides RosaicLabs with Atom RTL as Linux Posts Describe 32-Tile AMX x86 Implementations DevFeed: [Intel Reportedly Provides RosaicLabs with Atom RTL as Linux Posts Describe 32-Tile AMX x86 Implementations]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-07-31T01:39:23Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [Atom](), [x86](), [intel](), [cpu]() Tags: [cpu](), [intel](), [processor](), [x86]() ### AI overview The article examines reports that Intel is providing RosaicLabs with register-transfer-level code for Atom CPU technology, alongside Linux kernel posts describing x86 implementations with 16 and 32 AMX tile registers. It distinguishes reported facts from speculation linking the startup to the implementation. ### Source excerpt Hello you fine Internet folks, ## Payment Gateway vs Payment Processor: What's the Actual Difference? DevFeed: [Payment Gateway vs Payment Processor: What's the Actual Difference?]() Original publisher: [Read original article]() Author: Aarthi Poonia Published: 2026-06-06T00:00:00Z Content type: article Language: en Sources: [Dodo Payments Blog]() Topics: [Software as a service](), [stripe](), [API](), [tokenization](), [dashboards]() Tags: [api](), [authorization](), [chargebacks](), [checkout](), [gateway](), [glossary](), [payments](), [processor](), [saas](), [stripe](), [tokenization]() ### AI overview This guide explains the historical distinction between payment gateways and payment processors. Gateways handle checkout, encryption, tokenization, and routing, while processors handle authorization, settlement, funding, chargebacks, and refunds. Modern providers such as Stripe, PayPal, Square, and Adyen commonly combine both roles into one platform. ### Source excerpt Payment gateway vs payment processor explained. Where the line is drawn, why most modern providers do both, and what SaaS founders should actually care about. ## Stripe vs Square: Which Payment Processor Should You Choose in 2026? DevFeed: [Stripe vs Square: Which Payment Processor Should You Choose in 2026?]() Original publisher: [Read original article]() Author: Aarthi Poonia Published: 2026-06-01T00:00:00Z Content type: comparison Language: en Sources: [Dodo Payments Blog]() Topics: [stripe](), [API](), [Transactions](), [Software as a service]() Tags: [2026](), [api](), [billing](), [comparison](), [comparisons](), [developer](), [e-commerce](), [payment](), [payment-processing](), [pricing](), [processor](), [saas](), [stripe](), [subscriptions](), [terminal](), [vs]() ### AI overview A comparison of Stripe and Square for businesses choosing between payment processors. It examines pricing, online and in-person payments, subscriptions, international support, developer experience, and total cost of ownership, with the online-versus-in-person business model as a central decision factor. ### Source excerpt Stripe vs Square compared on pricing, features, online vs in-person payments, subscriptions, international support, and which one fits your business model. ## Payment Processing for Small Business: A Beginner's Guide DevFeed: [Payment Processing for Small Business: A Beginner's Guide]() Original publisher: [Read original article]() Author: Ayush Agarwal Published: 2026-04-13T00:00:00Z Content type: tutorial Language: en Sources: [Dodo Payments Blog]() Topics: [Transactions]() Tags: [beginner](), [chargebacks](), [compliance](), [fees](), [gateway](), [guide](), [merchant-of-record](), [payment-gateway](), [payment-processing](), [payments](), [pricing](), [processor](), [small-business](), [tax](), [us]() ### AI overview A beginner-friendly guide explains how online payment processing moves money between customers and businesses, identifies the main parties involved, outlines flat-rate, interchange-plus, and merchant-of-record pricing, and describes related services and costs. ### Source excerpt A plain-language guide to payment processing for small businesses - how it works, what fees to expect, and how to choose the right processor for your needs. ## CockroachDB Plans Native X.509 SAN Support for SPIFFE and SPIRE Integration DevFeed: [CockroachDB Plans Native X.509 SAN Support for SPIFFE and SPIRE Integration]() Original publisher: [Read original article]() Author: Sanchit Khanna,Biplav Saraf Published: 2026-03-13T00:00:00Z Content type: article Language: en Sources: [Cockroach Labs]() Topics: [CockroachDB](), [Databases](), [SPIFFE](), [SPIRE](), [certificates](), [Zero Trust](), [Security](), [Microservice]() Tags: [architectures](), [auditability](), [aws-iam](), [certificates](), [cockroachdb](), [compliance](), [cryptographic](), [database](), [distributed](), [processor](), [regex](), [security](), [soc](), [soc-2](), [spiffe](), [spire](), [standards](), [teams](), [verification](), [zero-trust]() ### AI overview The article previews planned CockroachDB authentication support for Subject Alternative Name fields in X.509 certificates. It explains how SAN support is intended to enable integration with SPIFFE and SPIRE and support regex-based identity mapping for cloud-native workloads. ### Source excerpt In the evolution of cloud-native security, identity has become the new perimeter. ## Prefix sums at tens of gigabytes per second with ARM NEON DevFeed: [Prefix sums at tens of gigabytes per second with ARM NEON]() Original publisher: [Read original article]() Author: Daniel Lemire Published: 2026-03-08T20:09:48Z Content type: tutorial Language: en Sources: [Daniel Lemire]() Topics: [systems](), [Arm](), [cpu](), [C]() Tags: [arm](), [c](), [cpu](), [processor]() ### AI overview The article explains how prefix sums can be optimized with ARM NEON SIMD instructions. It compares scalar and vector approaches and describes processing interleaved blocks of 16 integers in parallel to reduce the sequential instruction cost. ### Source excerpt Suppose that you have a record of your sales per day. You might want to get a running record where, for each day, you are told how many sales you have made since the start of the year. day sales per day running sales 1 10$ 10 $ 2 15$ 25 $ 3 5$ 30 ... Continue reading Prefix sums at tens of gigabytes per second with ARM NEON ## Getting Friendly With CPU Caches DevFeed: [Getting Friendly With CPU Caches]() Original publisher: [Read original article]() Published: 2025-10-21T00:00:00Z Content type: tutorial Language: en Sources: [William Kennedy]() Topics: [CPU Cache](), [Go Language](), [Data structures](), [Programming](), [Hardware](), [Caching]() Tags: [cache](), [cpu](), [data](), [data-structures](), [efficiency](), [go](), [golang](), [hardware](), [intel](), [latency](), [memory](), [performance](), [processor](), [programming](), [speed]() ### AI overview This tutorial explains how CPU cache behavior and data locality affect application performance. Using a Go case study, it shows that replacing a large embedded array in a user struct with a slice reduced cache misses and improved benchmark performance by more than 40 times. ### Source excerpt Understanding how your data structures interact with hardware is one of the most powerful ways to improve application performance. This blogpost explores how CPU caches influence speed and how thoughtful struct design in Go can yield massive gains. Through a real-world case study, it shows how replacing a large embedded array with a slice improved performance by more than 40 times by reducing cache misses and improving data locality. Originally published in July 2023, its lessons remain highly relevant today for developers optimizing for memory efficiency and cache-aware programming. ## Floating-Point Units on Espressif SoCs: Why (and when) they matter DevFeed: [Floating-Point Units on Espressif SoCs: Why (and when) they matter]() Original publisher: [Read original article]() Author: John Lee Published: 2025-10-13T00:00:00Z Content type: article Language: en Sources: [Blog on Developer Portal]() Topics: [Espressif](), [Hardware](), [cpu](), [ESP32-S3](), [ESP32-C3](), [Benchmark](), [math]() Tags: [benchmark](), [blog](), [esp32](), [esp32-c3](), [esp32-s3](), [espressif](), [floating-point](), [fpu](), [hardware](), [math](), [performance](), [precision](), [processor]() ### AI overview This article explains what floating-point units are, why they matter for calculations involving decimal values and wide dynamic ranges, and how they differ across Espressif SoCs. It states that the ESP32-S3 performs floating-point operations directly in hardware, while the ESP32-C3 executes them in software, and introduces a benchmark-based discussion of performance. ### Source excerpt In this article, you'll learn what an FPU is, why it's useful, which Espressif SoCs feature one, and how it impacts performance through a benchmark. ## Intel N100 Mini PC for R&D and Self-Hosting Compared with Raspberry Pi 5 DevFeed: [Intel N100 Mini PC for R&D and Self-Hosting Compared with Raspberry Pi 5]() Original publisher: [Read original article]() Author: Alex Ellis Published: 2025-08-18T08:09:48Z Content type: opinion Language: en Sources: [Alex Ellis' Blog]() Topics: [pc](), [intel](), [cpu](), [Self-hosted](), [Raspberry Pi](), [NVMe](), [Firecracker](), [Kubernetes](), [Linux](), [k3s](), [OpenFaaS](), [ddr5]() Tags: [ddr5](), [firecracker](), [github-actions](), [intel](), [k3s](), [kubernetes](), [linux](), [m-2-nvme](), [mini-pc](), [pc](), [processor](), [self-hosting](), [storage](), [threads](), [work]() ### AI overview The article evaluates the low-power Intel N100 Mini PC for R&D and self-hosting, comparing it with the Raspberry Pi 5. It discusses CPU, RAM, NVMe storage, Ethernet, virtualization, Kubernetes, Firecracker, and cost considerations. ### Source excerpt Exploring the capabilities of the Intel N100 Mini PC for work and self-hosting as an alternative to public cloud. ## Memory Profiling Part 2. Memory Usage Case Study DevFeed: [Memory Profiling Part 2. Memory Usage Case Study]() Original publisher: [Read original article]() Author: Denis Bakhvalov Published: 2024-02-12T05:00:00Z Content type: tutorial Language: en Sources: [Denis Bakhvalov]() Topics: [Benchmark](), [Linux](), [Ubuntu](), [Windows](), [cpu](), [intel]() Tags: [benchmark](), [book-chapters](), [case-study](), [intel](), [linux](), [performance-analysis](), [processor](), [profiling](), [ubuntu](), [windows]() ### AI overview This article presents a memory-usage case study of Stockfish's built-in benchmark using heaptrack on Linux, with comparisons to Mtuner on Windows. It examines memory consumption and allocation patterns, including long-lived and temporary allocations. ### Source excerpt Subscribe to my newsletter, support me on Patreon or by PayPal donation. Now, let's take a look at how to profile the memory usage of a real-world application. We will use heaptrack, an open-sourced heap memory profiler for Linux developed by KDE. Ubuntu users can install it very easily with . Heaptrack can find places in the code where the largest and most frequent allocations happen among many other things. On Windows, you can use Mtuner which has similar1 capabilities as Heaptrack. ## 2022 intern projects include sampling support for magic-trace DevFeed: [2022 intern projects include sampling support for magic-trace]() Original publisher: [Read original article]() Author: Yaron Minsky Published: 2022-08-25T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [Development](), [Traces](), [Open Source](), [intel](), [Processes](), [Testing]() Tags: [analysis](), [command-line](), [google](), [intel](), [internship](), [open-source](), [perfetto](), [performance](), [process](), [processor](), [traces]() ### AI overview The article highlights projects completed during Jane Street's 2022 internship season. It describes sampling support added to the open-source magic-trace tool, along with work integrating Datafetcher with Incremental and improving Quickcheck's contract syntax. ### Source excerpt We're once again at the end of our internship season, and it's my task to provide a few highlights of what the interns accomplished while they were here. ## Magic-trace: Diagnosing tricky performance issues easily with Intel Processor Trace DevFeed: [Magic-trace: Diagnosing tricky performance issues easily with Intel Processor Trace]() Original publisher: [Read original article]() Author: Tristan Hume Published: 2022-01-11T00:00:00Z Content type: article Language: en Sources: [Jane Street]() Topics: [tracing](), [Latency](), [cpu](), [Hardware](), [systems](), [Instrumentation](), [OCaml](), [Google]() Tags: [flow](), [instrumentation](), [intel](), [latency](), [ocaml](), [performance](), [processor](), [trace](), [tracing](), [visualization]() ### AI overview Jane Street describes magic-trace, an open-source tool built on Intel Processor Trace. It captures roughly 10 milliseconds of execution leading up to a selected function call and visualizes the call stack on a timeline, helping diagnose fine-grained performance and latency issues that sampling profilers may miss. ### Source excerpt Intel Processor Trace is a hardware technology that can record all program execution flow along with timing information accurate to around 30ns. As far as I can tell almost nobody uses it, seemingly because capturing the data is tricky and, without any visualization tools, you're forced to read enormous text dumps. ## A Close Look at a Spinlock DevFeed: [A Close Look at a Spinlock]() Original publisher: [Read original article]() Author: regehr Published: 2021-11-06T19:57:06Z Content type: article Language: en Sources: [Embedded in Academia]() Topics: [Concurrency](), [Concurrent Programming](), [Operating system](), [Algorithms](), [Code](), [Hardware](), [x86]() Tags: [algorithms](), [architecture](), [code](), [gcc](), [hardware](), [implementation](), [processor](), [synchronization](), [threads](), [uncategorized](), [x86]() ### AI overview This article explains how spinlocks provide mutual exclusion on multiprocessor systems. It covers why naive load-and-store implementations can fail on modern weak-memory architectures, how GCC atomic intrinsics can implement a portable user-mode spinlock, and how FIFO spinlocks can improve fairness under contention. ### Source excerpt The spinlock is the most basic mutual exclusion primitive provided by a multiprocessor operating system. Spinlocks need to protect against preemption on the current CPU (typically by disabling interrupts, but we'll ignore that aspect in this post) and also against attempts by other cores to concurrently access the critical section (by using atomic memory operations). [...] ## Welcome GSoC 2021 Students! DevFeed: [Welcome GSoC 2021 Students!]() Original publisher: [Read original article]() Published: 2021-05-18T00:00:00Z Content type: news Language: en Sources: [Front Page on ReactOS Website]() Topics: [ReactOS](), [Windows](), [Library](), [Hardware](), [Concurrency]() Tags: [concurrency](), [free](), [google-summer-of-code](), [gsoc](), [mentoring](), [open-source](), [os](), [processor](), [react](), [reactos](), [student](), [win32](), [winapi](), [windows]() ### AI overview The ReactOS Project is participating in Google Summer of Code 2021 and selected He Yang and Justin Miller for projects involving RunOnceEx support in iernonce.dll and Symmetric Multiprocessing support. The work is intended to improve compatibility, hardware usability, and concurrency handling in ReactOS. ### Source excerpt Another year, another round of Google Summer of Code! The ReactOS Project is participating in Google Summer of Code 2021 and welcomes the selected students. He Yang is a successful student from GSoC 2020, who is going to continue his dive into user-mode ReactOS this year by working on iernonce.dll. That library is responsible for RunOnceEx, a prominent Windows feature to run multiple commands once after a system reboot. Implementing that feature will benefit software depending on it. ## Modifying a THICC-15 Laptop for Android Development DevFeed: [Modifying a THICC-15 Laptop for Android Development]() Original publisher: [Read original article]() Author: Dmitry Samoylenko Published: 2021-04-01T00:00:00Z Content type: article Language: en Sources: [Dmitry Samoylenko - Android Developer Blog]() Topics: [Development](), [android-development](), [cpu]() Tags: [android-development](), [development](), [heat](), [internals](), [laptop](), [processor]() ### AI overview A hands-on account of modifying a THICC-15 laptop for Android development. The author adds a desktop Ryzen 9 3950X, cuts an opening in the cover, installs mesh ventilation, and adds copper cooling plates and thermal paste to improve portability and cooling. ### Source excerpt Or a Laptop for Android Development First step - we buy this chunky guy Update: on their site, only the full version with internals THICC-15 is left [Next page]()