# Processors Published articles for Processors. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## AMD Sends Out Linux Patches For Enabling SEV-TIO TDISP With PCIe 6.0 DevFeed: [AMD Sends Out Linux Patches For Enabling SEV-TIO TDISP With PCIe 6.0]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-09-16T13:02:52Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [pcie](), [trusted-execution-environment](), [Confidential Computing](), [virtualization](), [Security](), [Encryption](), [MERN]() Tags: [amd](), [arm](), [attestation](), [confidential-computing](), [cpu](), [desktop-linux](), [encryption](), [intel](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-kernel](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [pcie](), [phoronix](), [phoronix-test-suite](), [processors](), [risc-v](), [security](), [ubuntu-benchmarks](), [ubuntu-hardware]() ### AI overview AMD submitted 17 Linux kernel patches to enable SEV-TIO TDISP for PCIe 6.0 and newer. The work is intended to secure direct I/O device assignment for confidential-computing environments, including AMD Secure Encrypted Virtualization guest VMs, and includes a common TEE Security Manager developed with Intel, Arm, and RISC-V. ### Source excerpt The newest Linux kernel patches out of AMD for enhancing the upstream support with the new AMD EPYC 9006 "Venice" processors is for enabling SEV-TIO TDISP that is supported with PCI Express 6.0 and beyond... ## Subnormal floating-point numbers are expensive... on Intel processors DevFeed: [Subnormal floating-point numbers are expensive... on Intel processors]() Original publisher: [Read original article]() Author: Daniel Lemire Published: 2026-09-15T12:54:32Z Content type: article Language: en Sources: [Daniel Lemire]() Topics: [floating-point](), [Benchmark](), [intel](), [C++](), [Cache]() Tags: [benchmark](), [c-plus-plus](), [floating-point](), [intel](), [linux](), [numbers](), [performance](), [processors]() ### AI overview This article benchmarks the performance cost of IEEE subnormal floating-point values across Intel, AMD, Arm, and Apple processors. It reports that Intel multiplications involving subnormals can be about 45 to 50 times slower than normal multiplications, while additions and subtractions remain at full speed. AMD Zen 5 performs much better in the tested workloads. ### Source excerpt We represent floating-point numbers using the IEEE standard. For very small numbers, the standard uses special subnormal numbers. Unfortunately, they have a reputation of making operations slow. Thus video game programmers and machine learning specialists sometimes avoid computing with subnormal numbers for performance. How slow are they? Let me measure. I wrote a small C++ ... Continue reading Subnormal floating-point numbers are expensive... on Intel processors ## Linux Patch Coming To Fix Under-Reported AMD Zen 5 TLB Sizes DevFeed: [Linux Patch Coming To Fix Under-Reported AMD Zen 5 TLB Sizes]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-09-15T10:05:51Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux](), [cpu](), [x86](), [Kernel]() Tags: [amd](), [cpu](), [desktop-linux](), [issue](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-kernel](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [processors](), [reporting](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86]() ### AI overview A Linux kernel patch corrects under-reported Translation Lookaside Buffer sizes for AMD Zen 5 EPYC and Ryzen processors. The change also supports Zen 6 and future AMD CPUs using the same reporting bit. ### Source excerpt A minor reporting issue on Linux that has gone unaddressed until now is for properly conveying the Translation Lookaside Buffer (TLB) sizes on AMD Zen 5 processors... ## AMD Preparing Linux For Enhanced SMT Protection "ESMTP" For EPYC VMs DevFeed: [AMD Preparing Linux For Enhanced SMT Protection "ESMTP" For EPYC VMs]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-09-14T18:03:38Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux](), [Security](), [Hardware](), [cpu](), [Server](), [Cloud]() Tags: [attacks](), [cloud](), [desktop-linux](), [hardware](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [performance](), [phoronix](), [phoronix-test-suite](), [processors](), [security](), [server](), [ubuntu-benchmarks](), [ubuntu-hardware](), [virtual-machines]() ### AI overview AMD engineers are preparing Linux kernel support for Enhanced SMT Protection (ESMTP), a hardware-enforced security feature for EPYC virtual machines using SEV-SNP. ESMTP restricts simultaneous multithreading sibling threads to trusted vCPUs from the same guest or idle host threads, reducing side-channel risks from untrusted host or guest workloads. Support is also needed in QEMU and OVMF, and the feature is opt-in because it has a performance cost. ### Source excerpt AMD engineers today sent out patches on the Linux kernel mailing list for beginning to enable Enhanced SMT Protection "ESMTP" for better security with virtual machines running atop EPYC server processors with SEV-SNP... ## Infineon RISC-V for Automotive at Hot Chips 2026 DevFeed: [Infineon RISC-V for Automotive at Hot Chips 2026]() Original publisher: [Read original article]() Author: Vic A Published: 2026-09-13T21:58:44Z Content type: article Language: en Sources: [ServeTheHome]() Topics: [RISC-V](), [Microcontroller](), [real-time](), [Low Latency](), [Architecture & Design](), [Security](), [IO](), [Inference Performance]() Tags: [2026](), [architecture](), [automotive](), [compute](), [cost](), [efficiency](), [infineon](), [latency](), [low-latency](), [microcontrollers](), [mobile](), [performance](), [posix](), [processors](), [real-time](), [risc-v](), [security]() ### AI overview Infineon presents RISC-V automotive processors for next-generation vehicle architectures. The article covers real-time control, low latency, power efficiency, security, zone controllers, central car computers, and heterogeneous workloads including DSP, AI inference, audio, and POSIX-based services. ### Source excerpt At Hot Chips 2026, Infineon presented a case for using RISC-V in various automotive processors in next-generation cars The post Infineon RISC-V for Automotive at Hot Chips 2026 appeared first on ServeTheHome. ## New Cache Aware Scheduling Fixes Out For Testing DevFeed: [New Cache Aware Scheduling Fixes Out For Testing]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-09-11T18:00:14Z Content type: news Language: en Sources: [Phoronix]() Topics: [Cache](), [Linux](), [cpu](), [intel](), [Latency]() Tags: [cache](), [cpu](), [desktop-linux](), [feature](), [intel](), [kernel](), [latency](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [processors](), [series](), [testing](), [ubuntu-benchmarks](), [ubuntu-hardware]() ### AI overview New fixes to Linux kernel Cache Aware Scheduling are available for testing on Intel hybrid CPUs. The patches address tasks being stranded or moved away from their preferred last-level cache, along with a use-after-free issue, while known interference with Intel Turbo Boost Max Technology remains unresolved. ### Source excerpt Since being merged back during the Linux 7.2 cycle, the Cache Aware Scheduling code continues seeing more fixes as users test out this scheduling enhancement on different processors and system configurations... ## ASUS Pro WS W890E-SAGE SE Motherboard Review DevFeed: [ASUS Pro WS W890E-SAGE SE Motherboard Review]() Original publisher: [Read original article]() Author: Ryan Smith Published: 2026-09-11T17:00:36Z Content type: article Language: en Sources: [ServeTheHome]() Topics: [Hardware](), [intel]() Tags: [10gbe](), [asus](), [e610](), [hardware](), [intel](), [motherboard](), [processors](), [review](), [workstation](), [workstation-motherboards](), [xeon-600]() ### AI overview A review of ASUS's Pro WS W890E-SAGE SE, a premium workstation motherboard for Intel's Xeon 600 platform. It examines the board's support for the W890 chipset, eight-channel memory, extensive I/O, BMC functionality, and overclocking features. ### Source excerpt Today we are taking a look at ASUS's premium motherboard for the new Xeon 600 workstation platform, the Pro WS W890E-SAGE SE. A showcase for the platform, the SAGE SE supports Xeon 600's full capabilities, while looking to appeal to both businesses and enthusiasts alike The post ASUS Pro WS W890E-SAGE SE Motherboard Review appeared first on ServeTheHome. ## IBM Quantum System Two Heads to Switzerland: 120-Qubit Nighthawk r2 at CSCS by End of 2026 DevFeed: [IBM Quantum System Two Heads to Switzerland: 120-Qubit Nighthawk r2 at CSCS by End of 2026]() Original publisher: [Read original article]() Author: Harold Fritts Published: 2026-09-11T16:25:47Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [ibm](), [Quantum Computing](), [Supercomputing](), [Cloud](), [Algorithms](), [Optimization](), [Simulation and Design](), [Hardware]() Tags: [2026](), [ai](), [algorithms](), [amd](), [chemistry](), [cloud](), [collaboration](), [core](), [enterprise](), [financial-services](), [hardware](), [hub](), [ibm](), [infrastructure](), [manufacturing](), [optimization](), [processors](), [quantum](), [quantum-computing](), [science](), [simulation](), [supercomputing]() ### AI overview IBM and Lockheed Martin are establishing a quantum innovation hub at ETH Zurich, centered on an IBM Quantum System Two planned for installation at the Swiss National Supercomputing Centre by the end of 2026. The system will use IBM's 120-qubit Nighthawk r2 processor and support research in areas including chemistry, materials science, optimization, and financial services. ### Source excerpt IBM and Lockheed Martin are setting up a quantum innovation hub at ETH Zurich, and its core is Switzerland's first IBM Quantum System Two, to be installed at the Swiss National Supercomputing Centre (CSCS) in Lugano by the end of 2026. The hub comes out of an offset agreement with armasuisse, Switzerland's Federal Office for The post IBM Quantum System Two Heads to Switzerland: 120-Qubit Nighthawk r2 at CSCS by End of 2026 appeared first on StorageReview.com. ## Arm CSS for Mobile 2 "AI-Native" platform: Arm C2-Ultra and C2-Pro CPU cores, Mali G2-Ultra NX GPU DevFeed: [Arm CSS for Mobile 2 "AI-Native" platform: Arm C2-Ultra and C2-Pro CPU cores, Mali G2-Ultra NX GPU]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-08T02:52:39Z Content type: article Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Arm](), [cpu](), [Artificial Intelligence](), [GPU](), [Embedded Systems]() Tags: [ai](), [arm](), [armv9](), [artificial-intelligence-ai](), [benchmarks](), [cpu](), [embedded-systems](), [gpu](), [laptop](), [processors](), [smartphone]() ### AI overview Arm introduced the CSS for Mobile 2 platform, combining C2-Ultra and C2-Pro CPUs with SME2 units and the Mali G2-Ultra NX GPU with dedicated neural accelerators. The article covers their specifications and Arm's claimed performance improvements over the previous C1 generation. ### Source excerpt Arm has introduced the CSS for Mobile 2 platform as an AI-native compute foundation comprised of the Arm C2-Ultra and C2-Pro CPUs with SME2 (Scalable Matrix Extension 2) units and the Mali G2-Ultra NX GPU with dedicated neural accelerators that enable neural graphics to run natively on the GPU. Arm C2-Ultra and C2-Pro CPUs Arm C2-Ultra specifications: Architecture - Armv9.3-A Extensions Armv9.4-A (Some key features) SME2 Extensions SVE2 Extensions Cryptography Extensions RAS Extensions ISA support - AArch64 Microarchitecture Pipeline - Out-of-order Superscalar Neon and SVE2 Optional Cryptography Unit Up to 14x CPUs in cluster 40-bit Physical Addressing Memory System and External Interfaces 64KB (I-Cache), 128KB (D-Cache) 2MB or 3MB L2 Cache Optional, 256KB to 32MB L3 Cache ECC Support Bus interfaces - AMBA AXI5 or CHI.E Optional ACP Optional Peripheral Port Security - TrustZone, Secure-EL2 Interrupts - GIC interface, GICv4.1 PMU - PMUv3 CoreSight - CoreSightv3 Embedded Trace Extension - [...] The post Arm CSS for Mobile 2 "AI-Native" platform: Arm C2-Ultra and C2-Pro CPU cores, Mali G2-Ultra NX GPU appeared first on CNX Software - Embedded Systems News. ## Artery AT32F406 and AT32F408 Cortex-M4F MCUs feature optional high-speed USB OTG PHY DevFeed: [Artery AT32F406 and AT32F408 Cortex-M4F MCUs feature optional high-speed USB OTG PHY]() Original publisher: [Read original article]() Author: Debashis Das Published: 2026-09-03T09:40:39Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Microcontroller](), [Embedded Systems](), [Arm](), [USB](), [Internet of things](), [cpu](), [Hardware]() Tags: [arm](), [boot](), [bootloader](), [c-c-plus-plus](), [cortex-m4](), [cpu](), [development-board](), [embedded](), [embedded-systems](), [hardware](), [industrial](), [iot](), [mcu](), [microcontrollers](), [processors](), [specifications](), [usb]() ### AI overview The article describes Artery Technology's AT32F406 and AT32F408 Arm Cortex-M4F microcontrollers, which run at up to 216 MHz. The AT32F408 adds USB 2.0 OTG High-Speed support with an integrated PHY, while both devices provide DSP and floating-point capabilities, configurable memory options, QSPI, and a range of digital and analog peripherals. ### Source excerpt Artery Technology AT32F406 and AT32F408 are two new Arm Cortex-M4F MCUs running at up to 216 MHz, with the F408 adding USB OTG High-Speed and an integrated PHY for industrial automation, IoT, USB accessories, and gaming peripherals. The AT32F406/F408 series both offer DSP instructions and a floating-point unit (FPU), integrate up to 512 KB Flash and 192 KB SRAM, and a 4 KB OTP memory for critical data and parameters. The microcontrollers also offer a QSPI interface for external Flash or RAM expansion, and a range of digital and analog peripheral interfaces. Artery AT32F406/AT32F408 specifications: MCU - 32-bit Arm Cortex-M4F CPU up to 216 MHz; also features Memory Protection Unit (MPU) and DSP instructions Memory/Storage 128 KB to 192 KB SRAM 256 KB to 512 KB Flash memory 26 KB boot memory (configurable as a bootloader or general instruction/data memory) 4 KB OTP (one-time programmable) memory QSPI interface for external SPI [...] The post Artery AT32F406 and AT32F408 Cortex-M4F MCUs feature optional high-speed USB OTG PHY appeared first on CNX Software - Embedded Systems News. ## AWS Launches Graviton5-Based EC2 R9g and R9gd Memory-Optimized Instances DevFeed: [AWS Launches Graviton5-Based EC2 R9g and R9gd Memory-Optimized Instances]() Original publisher: [Read original article]() Author: Harold Fritts Published: 2026-09-01T18:42:59Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [Amazon Web Services](), [Amazon EC2](), [Arm](), [cpu](), [Hardware](), [Nitro System](), [virtualization](), [Nitro Isolation Engine](), [Database](), [Caching](), [Kubernetes](), [Formal verification]() Tags: [amazon-ec2](), [amazon-eks](), [arm](), [aws](), [c-plus-plus](), [caching](), [cloud](), [database](), [docker](), [enterprise](), [formal-verification](), [go](), [hardware](), [java](), [microservices](), [nitro-isolation-engine](), [nitro-system](), [node-js](), [nvme](), [processors](), [python](), [time]() ### AI overview AWS has generally released the Amazon EC2 R9g and R9gd instances, powered by AWS Graviton5 processors. These Arm-based, memory-optimized instances offer higher per-vCPU performance, faster memory, larger cache capacity, and increased networking and Amazon EBS bandwidth for database, caching, analytics, container, and microservices workloads. R9gd adds local NVMe SSD storage for low-latency local capacity. Both families use the AWS Nitro System and Nitro Isolation Engine, with AWS citing formal verification for the isolation properties. ### Source excerpt AWS has made its Amazon EC2 R9g and R9gd instances generally available, introducing memory-optimized systems powered by AWS Graviton5 processors. The new Arm-based instances target database, caching, analytics, container, and microservices workloads that require high memory bandwidth and improved per-vCPU performance. Compared with Graviton4-based R8g instances, AWS states that R9g can deliver up to 25% The post AWS Launches Graviton5-Based EC2 R9g and R9gd Memory-Optimized Instances appeared first on StorageReview.com. ## D-Robotics RDK S100P - A 128 TOPS alternative to NVIDIA Jetson Orin NX 16GB with Cortex-A78AE/R52+ cores DevFeed: [D-Robotics RDK S100P - A 128 TOPS alternative to NVIDIA Jetson Orin NX 16GB with Cortex-A78AE/R52+ cores]() Original publisher: [Read original article]() Author: Debashis Das Published: 2026-08-31T08:06:13Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Jetson](), [Robotics](), [Embedded Systems](), [Microcontroller](), [Jetson Orin](), [SOC](), [cpu](), [Arm](), [real-time](), [GPU](), [Linux](), [Nvidia]() Tags: [arm](), [artificial-intelligence-ai](), [camera](), [computer-vision](), [cortex-a78](), [cpu](), [deep-learning](), [development-kit](), [dfrobot](), [edge-ai](), [embedded](), [embedded-systems](), [gpu](), [hardware](), [jetson](), [jetson-orin](), [linux](), [mcu](), [networking](), [nvidia](), [os](), [processors](), [real-time](), [robotics](), [ros](), [safety](), [sensor](), [sensors](), [single-board-computer](), [soc](), [software](), [som](), [specifications](), [systems](), [ubuntu]() ### AI overview The D-Robotics RDK S100P is a robotics single-board computer featuring a 6-core Cortex-A78AE CPU, 4-core Cortex-R52+ MCU domain, 128 TOPS INT8 Nash BPU, Mali-G78AE GPU, and 24 GB of LPDDR5. Its MCU supports real-time motor and sensor control, potentially reducing the need for a separate real-time controller depending on the robot's requirements. ### Source excerpt D-Robotics RDK S100P development kit is a robotics SBC built around an S100P-based module providing an alternative to NVIDIA Jetson Orin NX 16GB with a 6-core Cortex-A78AE application cluster, a 4-core Cortex-R52+ MCU domain, a Nash BPU rated at 128 TOPS INT8, a Mali-G78AE GPU, and 24 GB of LPDDR5. The four R52+ cores can be configured for reliable real-time control: two cores run in lockstep for safety, and the other two support split-lock operation. In practice, the A78AE CPU and BPU can handle Linux and vision processing, while the MCU handles time-critical tasks such as motor and sensor I/O. This can reduce the need for a separate real-time controller, although whether it eliminates one depends on the robot and its requirements. RDK S100P specifications: SoC - D-Robotics S100P CPU - 6x Arm Cortex-A78AE @ 2.0 GHz (safety-capable AE cores) MCU - 4x Arm Cortex-R52+ @ 1.2 GHz (1x DCLS [...] The post D-Robotics RDK S100P - A 128 TOPS alternative to NVIDIA Jetson Orin NX 16GB with Cortex-A78AE/R52+ cores appeared first on CNX Software - Embedded Systems News. ## Performance Progression of Percona Server for MySQL 8.4 DevFeed: [Performance Progression of Percona Server for MySQL 8.4]() Original publisher: [Read original article]() Author: Bogdan Degtyariov Published: 2026-08-27T13:07:20Z Content type: article Language: en Sources: [Blog - Percona]() Topics: [MySQL](), [benchmarking](), [Benchmark](), [Scalability](), [configuration](), [cpu](), [Hardware]() Tags: [2026](), [benchmark](), [benchmarking](), [benchmarks](), [concurrency](), [configuration](), [cpu](), [data](), [database](), [hardware](), [intel](), [latency](), [load](), [measurement](), [mysql](), [percona](), [percona-server-for-mysql](), [performance](), [processors](), [run]() ### AI overview This article investigates read/write performance changes across Percona Server for MySQL 8.4 versions released in 2026. It describes benchmark scope, database and buffer-size combinations, configuration, and CPU-frequency controls, while excluding features, security patches, latency percentiles, and resource-utilization measurements. ### Source excerpt 1. Purpose and scope This performance investigation aims to look into the read/write performance of Percona Server for MySQL 8.4 and how it changed between versions released in 2026: 8.4.8-8 released on 12 March 2026 8.4.10-10 released on 30 June 2026 8.4.11-11 released on 20 August 2026 We want to see if there are improvements ... Continued The post Performance Progression of Percona Server for MySQL 8.4 appeared first on Percona. ## Hot Chips 2026: Intel's Wildcat Lake DevFeed: [Hot Chips 2026: Intel's Wildcat Lake]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-24T19:50:30Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [intel](), [cpu](), [GPU](), [SOC](), [Bluetooth]() Tags: [2026](), [architecture](), [battery](), [bluetooth](), [core](), [cost](), [cpu](), [gpu](), [intel](), [platform](), [processors](), [soc](), [technologies](), [technology](), [wifi](), [wildcat-lake]() ### AI overview This article examines how Intel designed Wildcat Lake, also called Core Series 3, as a lower-cost mobile processor platform. It describes the use of new CPU cores, Xe3 graphics, IO, a multi-chip package, a distinct platform, and selected feature trade-offs to reduce costs while retaining capabilities important to battery life and connectivity. ### Source excerpt All about making things affordable ## AMD Instinct MI455X GPU Detailed for Rack-Scale AI Deployments DevFeed: [AMD Instinct MI455X GPU Detailed for Rack-Scale AI Deployments]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-07-23T17:37:10Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [GPU](), [Artificial Intelligence](), [networking](), [NVLink](), [systems](), [Ethernet](), [SOC](), [tsmc]() Tags: [2026](), [ai](), [architecture](), [article](), [capacity](), [communication](), [compute](), [ethernet](), [gpu](), [memory](), [networking](), [performance](), [processors](), [scale](), [soc](), [tsmc]() ### AI overview The article examines AMD's Instinct MI455X, a CDNA5 GPU designed for rack-scale AI deployments. It describes the Helios rack-scale system, UALink over Ethernet networking, compute and memory specifications, and changes to the WGP, register-file, and matrix-unit designs. ### Source excerpt Editor's Note (7/25/2026): The article has been edited with more information about the L2 behavior along with the bandwidth of the die to die interface. ## OTel-Arrow Phase 2: From Efficient Transport to Efficient Telemetry Pipelines DevFeed: [OTel-Arrow Phase 2: From Efficient Transport to Efficient Telemetry Pipelines]() Original publisher: [Read original article]() Author: OpenTelemetry Authors; Docs CC BY Published: 2026-06-13T00:47:46Z Content type: article Language: en Sources: [Blog on OpenTelemetry]() Topics: [OpenTelemetry](), [telemetry](), [Structured-data](), [systems](), [Rust](), [Instrumentation]() Tags: [apache-arrow](), [memory](), [opentelemetry](), [overhead](), [pipelines](), [processors](), [rust](), [telemetry]() ### AI overview This article presents Phase 2 of OTel-Arrow, which uses Apache Arrow not only for transport through OTAP but also as the internal representation of telemetry pipelines. It describes the Rust-based OTel-Arrow Dataflow Engine and reports substantially lower transport and processing costs when telemetry remains on the OTAP path end to end. ### Source excerpt Phase 1 of OTel-Arrow established OTAP, the OpenTelemetry Arrow Protocol, as an efficient transport protocol for OpenTelemetry. Apache Arrow is a language-independent, columnar in-memory format designed to move and process structured data efficiently across systems. We demonstrated that telemetry could be transported with significantly lower network overhead while preserving compatibility with the OpenTelemetry data model. Phase 2 asked a different question: what happens if Arrow is used not only on the wire, but also as the representation the pipeline works with internally? ## Stripe vs PayPal in 2026: Fees, Features, and Which One Wins for SaaS DevFeed: [Stripe vs PayPal in 2026: Fees, Features, and Which One Wins for SaaS]() Original publisher: [Read original article]() Author: Ayush Agarwal Published: 2026-06-02T00:00:00Z Content type: comparison Language: en Sources: [Dodo Payments Blog]() Topics: [stripe](), [Binance](), [Software as a service](), [API](), [Transactions]() Tags: [2026](), [api](), [checkout](), [comparisons](), [conversion](), [e-commerce](), [features](), [fees](), [payment-processing](), [payments](), [paypal](), [pricing](), [processors](), [saas](), [stripe](), [subscriptions](), [vs]() ### AI overview A 2026 comparison of Stripe and PayPal for SaaS, e-commerce, and digital product businesses. It examines processing fees, checkout, subscriptions, international transactions, payouts, and product capabilities, finding Stripe cheaper for the example $50 US online card transaction while noting PayPal's separate Braintree Direct pricing. ### Source excerpt Stripe vs PayPal compared in 2026 - processing fees, checkout conversion, subscriptions, international support, payouts, and which one to use for SaaS vs e-commerce. ## Matching JSON and whitespace characters efficiently on ARM processors DevFeed: [Matching JSON and whitespace characters efficiently on ARM processors]() Original publisher: [Read original article]() Author: Daniel Lemire Published: 2026-04-19T20:41:04Z Content type: article Language: en Sources: [Daniel Lemire]() Topics: [Arm](), [JSON](), [Parsing]() Tags: [amd](), [architecture](), [arm](), [ascii](), [avx](), [intel](), [json](), [parsing](), [processors]() ### AI overview The article examines vectorized classification for matching ASCII whitespace and structural JSON characters. It describes a branch-free NEON approach and discusses newer ARM Scalable Vector Extension instructions as an alternative on recent ARM processors. ### Source excerpt Consider the following problem. Given a string, you must match all of the ASCII white-space characters (\t, \n, \r, and the space) and some characters important in JSON (:, ,, [, ], {, }). JSON is a text-based data format used for web services. A toy JSON document looks as follows. { "name": "Alice", "age": ... Continue reading The fastest way to match characters on ARM processors? ## Payment Processing Fees Compared: Stripe vs PayPal vs Square vs Dodo DevFeed: [Payment Processing Fees Compared: Stripe vs PayPal vs Square vs Dodo]() Original publisher: [Read original article]() Author: Ayush Agarwal Published: 2026-04-14T00:00:00Z Content type: comparison Language: en Sources: [Dodo Payments Blog]() Topics: [stripe](), [Software as a service]() Tags: [2026](), [add-ons](), [billing](), [business](), [chargebacks](), [checkout](), [compare](), [comparison](), [fees](), [gateway](), [merchant-of-record](), [payment](), [payment-fees](), [payment-processing](), [payments](), [paypal](), [pricing](), [processors](), [saas](), [stripe](), [vs]() ### AI overview A June 2026 comparison of payment processing fees from Stripe, PayPal, Square, and Dodo. It separates domestic and international cards, subscriptions, disputes, and currency conversion, and explains how the best option varies by business type and payment route. ### Source excerpt Compare payment processing fees across Stripe, PayPal, Square, and Dodo in 2026, including headline rates, hidden add-ons, and which model fits different business types. ## How many branches can your CPU predict? DevFeed: [How many branches can your CPU predict?]() Original publisher: [Read original article]() Author: Daniel Lemire Published: 2026-03-18T21:52:53Z Content type: opinion Language: en Sources: [Daniel Lemire]() Topics: [cpu](), [benchmarking](), [Benchmark]() Tags: [amd](), [apple](), [benchmark](), [benchmarking](), [cpu](), [intel](), [processors](), [test]() ### AI overview A benchmark examines how many branch outcomes recent processors can learn when the same random values are repeated. AMD Zen 5 predicts 30,000 branches, Apple M4 predicts 10,000, and Intel Emerald Rapids predicts 5,000 in the reported test. ### Source excerpt Modern processors have the ability to execute many instructions per cycle, on a single core. To be able to execute many instructions per cycle in practice, processors predict branches. I have made the point over the years that modern CPUs have an incredible ability to predict branches. It makes benchmarking difficult because if you test ... Continue reading How many branches can your CPU predict? ## Beyond x86: Java on ARM in 2025 DevFeed: [Beyond x86: Java on ARM in 2025]() Original publisher: [Read original article]() Author: Artur Skowronski Published: 2025-12-05T02:02:36Z Content type: article Language: en Sources: [Java Advent Calendar]() Topics: [Arm](), [Java](), [x86](), [Cloud]() Tags: [2017](), [2025](), [architecture](), [arm](), [backend](), [cloud](), [java](), [processors](), [x86]() ### AI overview The article examines why Java on ARM is becoming more relevant for backend and server workloads in 2025. It discusses ARM's historical association with mobile and embedded devices, Apple's transition to ARM-based Macs, and the development of the Neoverse architecture for data centers, while noting the JVM ecosystem's gradual adaptation. ### Source excerpt We all know the mantra: "Write Once, Run Anywhere." But for most of Java's history, that "Anywhere" really meant "anywhere, as long as there's Intel or AMD underneath." When most of us were starting out with Java, ARM was something you associated with phones, a Raspberry Pi, or some mysterious "embedded" device - not with [...] The post Beyond x86: Java on ARM in 2025 appeared first on JVM Advent. ## Beyond the Single-Writer Limitation with Turso's Concurrent Writes DevFeed: [Beyond the Single-Writer Limitation with Turso's Concurrent Writes]() Original publisher: [Read original article]() Author: Pekka Enberg Published: 2025-10-06T00:00:00Z Content type: article Language: en Sources: [Turso Blog]() Topics: [Turso](), [SQLite](), [Concurrency](), [Concurrent Programming](), [Benchmark](), [Transactions](), [Database]() Tags: [benchmark](), [concurrency](), [concurrent](), [database](), [processors](), [sqlite](), [transactions](), [turso]() ### AI overview Turso announces a beta tech preview of concurrent writes that addresses SQLite's single-writer limitation. The article reports up to 4x SQLite's write throughput while avoiding the database-locked error caused by blocked concurrent writes. ### Source excerpt With multi-core processors and multi-threaded architectures becoming the norm, the old single-writer model that SQLite pioneered has started to show its age in today's concurrent world. ## Optimizing ClickHouse for Intel's ultra-high core count processors DevFeed: [Optimizing ClickHouse for Intel's ultra-high core count processors]() Original publisher: [Read original article]() Author: Jiebin Sun, Zhiguo Zhou, Wangyang Guo, Tianyou Li Published: 2025-09-17T00:00:00Z Content type: article Language: en Sources: [ClickHouse Blog]() Topics: [clickhouse](), [Optimization](), [Scalability](), [intel](), [cpu](), [Databases](), [systems]() Tags: [clickhouse](), [databases](), [hardware](), [intel](), [optimization](), [performance](), [processors](), [scalability](), [systems]() ### AI overview This guest article explains efforts to optimize ClickHouse for Intel ultra-high core count processors. It examines scalability challenges such as lock contention, cache coherence, NUMA, memory bandwidth, and coordination overhead, and reports performance improvements from systematic profiling and query-specific optimizations across 43 ClickBench queries. ### Source excerpt Intel's latest processor generations are pushing the number of cores in a server to unprecedented levels. For analytical databases like ClickHouse, ultra-high core counts represent a huge opportunity and a complex challenge. ## Underrust: How does u128 work on a 64-bit processor? DevFeed: [Underrust: How does u128 work on a 64-bit processor?]() Original publisher: [Read original article]() Author: Graham King Published: 2025-04-05T20:45:00Z Content type: tutorial Language: en Sources: [Graham King]() Topics: [cpu](), [x86](), [Rust](), [Compiler](), [Assembly](), [Code]() Tags: [assembly](), [code](), [compiler](), [processors](), [rust](), [simd](), [software](), [sse](), [underrust](), [x86]() ### AI overview The article explains how Rust u128 values work on x86-64 processors whose general-purpose registers are limited to 64 bits. It describes splitting values across two registers and distinguishes this from the use of 128-bit SSE registers for SIMD operations. ### Source excerpt Wherein our hero learns the arcane secrets of the u128 sword in the depths of the Underrust. [Next page]()