# Syracuse University

Published articles for Syracuse University.

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## Chip Industry Technical Paper Roundup: Oct. 6

DevFeed: [Chip Industry Technical Paper Roundup: Oct. 6](<https://devfeed.tech/articles/chip-industry-technical-paper-roundup-oct-6-65548.md>)

Original publisher: [Read original article](<https://semiengineering.com/chip-industry-technical-paper-roundup-oct-6/>)

Author: Linda Christensen

Published: 2026-10-06T07:01:55Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [High-Performance Computing](<https://devfeed.tech/topics/high-performance-computing.md>), [LLM Techniques](<https://devfeed.tech/topics/llm-techniques.md>)

Tags: [fau-erlangen-nurnberg](<https://devfeed.tech/tags/fau-erlangen-nurnberg.md>), [furiosaai](<https://devfeed.tech/tags/furiosaai.md>), [georgia-institute-of-technology](<https://devfeed.tech/tags/georgia-institute-of-technology.md>), [hong-kong-polytechnic-university](<https://devfeed.tech/tags/hong-kong-polytechnic-university.md>), [huazhong-university-of-science-and-technology](<https://devfeed.tech/tags/huazhong-university-of-science-and-technology.md>), [infineon-technologies](<https://devfeed.tech/tags/infineon-technologies.md>), [national-university-of-singapore](<https://devfeed.tech/tags/national-university-of-singapore.md>), [paper](<https://devfeed.tech/tags/paper.md>), [purdue-university](<https://devfeed.tech/tags/purdue-university.md>), [qatar-computing-research-institute](<https://devfeed.tech/tags/qatar-computing-research-institute.md>), [research](<https://devfeed.tech/tags/research.md>), [research-lphp](<https://devfeed.tech/tags/research-lphp.md>), [semiconductor-research](<https://devfeed.tech/tags/semiconductor-research.md>), [syracuse-university](<https://devfeed.tech/tags/syracuse-university.md>), [technical](<https://devfeed.tech/tags/technical.md>), [tu-dresden](<https://devfeed.tech/tags/tu-dresden.md>), [tu-munich](<https://devfeed.tech/tags/tu-munich.md>), [uc-berkeley](<https://devfeed.tech/tags/uc-berkeley.md>), [uc-santa-barbara](<https://devfeed.tech/tags/uc-santa-barbara.md>), [uc-santa-cruz](<https://devfeed.tech/tags/uc-santa-cruz.md>)

### AI overview

This roundup lists newly added semiconductor research papers on WSe₂ transistors, clock meshes for 2nm GAAFETs, DRAM processing, high-throughput LLM serving, CAN XL security analysis, and abstraction and validation from physical devices to RTL.

### Source excerpt

Low-contact-resistance WSe₂ transistors; backside clock meshes for 2nm GAAFETs; row-parallel processing in DRAM; HBF for high-throughput LLM serving; formal security analysis of CAN XL; abstraction and validation from physical devices to RTL. The post Chip Industry Technical Paper Roundup: Oct. 6 appeared first on Semiconductor Engineering.

## Row-Parallel DRAM Computing Cuts Data-Reorganization Overhead (Syracuse, FAU, TU Dresden)

DevFeed: [Row-Parallel DRAM Computing Cuts Data-Reorganization Overhead (Syracuse, FAU, TU Dresden)](<https://devfeed.tech/articles/row-parallel-dram-computing-cuts-data-reorganization-overhead-syracuse-fau-tu-dresden-64922.md>)

Original publisher: [Read original article](<https://semiengineering.com/row-parallel-dram-computing-cuts-data-reorganization-overhead-syracuse-fau-tu-dresden/>)

Author: Technical Paper Link

Published: 2026-10-05T18:16:28Z

Content type: article

Language: en

Sources: [Semiconductor Engineering](<https://devfeed.tech/sources/semiconductor-engineering.md>)

Topics: [Computing](<https://devfeed.tech/topics/computing.md>), [Memory Heirarchy](<https://devfeed.tech/topics/memory-heirarchy.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [ddr5](<https://devfeed.tech/topics/ddr5.md>)

Tags: [accelerators](<https://devfeed.tech/tags/accelerators.md>), [alex](<https://devfeed.tech/tags/alex.md>), [architectures](<https://devfeed.tech/tags/architectures.md>), [arxiv](<https://devfeed.tech/tags/arxiv.md>), [bit-parallel-arithmetic](<https://devfeed.tech/tags/bit-parallel-arithmetic.md>), [computing](<https://devfeed.tech/tags/computing.md>), [data](<https://devfeed.tech/tags/data.md>), [data-movement](<https://devfeed.tech/tags/data-movement.md>), [ddr4](<https://devfeed.tech/tags/ddr4.md>), [dram](<https://devfeed.tech/tags/dram.md>), [engineering](<https://devfeed.tech/tags/engineering.md>), [friedrich-alexander-universitat-erlangen-nurnberg](<https://devfeed.tech/tags/friedrich-alexander-universitat-erlangen-nurnberg.md>), [in-memory-computing](<https://devfeed.tech/tags/in-memory-computing.md>), [inversion-cells](<https://devfeed.tech/tags/inversion-cells.md>), [memory](<https://devfeed.tech/tags/memory.md>), [memory-architecture](<https://devfeed.tech/tags/memory-architecture.md>), [memory-bandwidth](<https://devfeed.tech/tags/memory-bandwidth.md>), [migration-cells](<https://devfeed.tech/tags/migration-cells.md>), [mlperf](<https://devfeed.tech/tags/mlperf.md>), [parallel](<https://devfeed.tech/tags/parallel.md>), [pim](<https://devfeed.tech/tags/pim.md>), [power-performance](<https://devfeed.tech/tags/power-performance.md>), [processing-in-memory](<https://devfeed.tech/tags/processing-in-memory.md>), [processing-using-memory](<https://devfeed.tech/tags/processing-using-memory.md>), [pum](<https://devfeed.tech/tags/pum.md>), [rapid](<https://devfeed.tech/tags/rapid.md>), [row-parallel-computing](<https://devfeed.tech/tags/row-parallel-computing.md>), [semiconductor](<https://devfeed.tech/tags/semiconductor.md>), [semiconductor-research](<https://devfeed.tech/tags/semiconductor-research.md>), [spice-simulation](<https://devfeed.tech/tags/spice-simulation.md>), [syracuse-university](<https://devfeed.tech/tags/syracuse-university.md>), [technical-papers](<https://devfeed.tech/tags/technical-papers.md>), [tu-dresden](<https://devfeed.tech/tags/tu-dresden.md>), [volatile-memory](<https://devfeed.tech/tags/volatile-memory.md>)

### AI overview

Researchers from Syracuse University, Friedrich-Alexander-Universität Erlangen-Nürnberg, and TU Dresden present RAPID, a processing-in-DRAM architecture. It uses migration cells for movement between neighboring bitlines and inversion cells for in-array logical inversion, enabling row-parallel, bit-parallel computation while preserving CPU-compatible data layouts.

### Source excerpt

Researchers at Syracuse University, Friedrich-Alexander-Universität Erlangen-Nürnberg, and TU Dresden published a technical paper titled "RAPID: Row-Parallel Arithmetic Processing in DRAM." Abstract Excerpt: "Processing-using-memory (PUM) architectures perform computation directly within DRAM to reduce costly data movement between memory and processors. Because charge-sharing operations are confined to individual bitlines, existing DRAM-PUM architectures reorganize data into column-oriented, bit-serial... " read more The post Row-Parallel DRAM Computing Cuts Data-Reorganization Overhead (Syracuse, FAU, TU Dresden) appeared first on Semiconductor Engineering.