# x86 Published articles for x86. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Why are we all worked up about atomicity when applying hot-patches if we can just suspend all the threads? DevFeed: [Why are we all worked up about atomicity when applying hot-patches if we can just suspend all the threads?]() Original publisher: [Read original article]() Author: Raymond Chen Published: 2026-11-06T15:00:00Z Content type: article Language: en Sources: [Raymond Chen]() Topics: [patches](), [synchronization]() Tags: [atomic](), [code](), [function](), [old-new-thing](), [patches](), [patching](), [process](), [processors](), [suspend](), [threads](), [time](), [update](), [variable](), [windows](), [windows-update](), [x86]() ### AI overview Atomic activation matters because suspending a process's existing threads does not prevent a new, runnable thread from being created with CreateRemoteThread while patching is underway. On processors with variable-length instructions such as x86, a suspended thread may also be poised to execute bytes that become the tail of a replacement instruction; the post says the original instruction must be at least as large as the replacement to avoid that case. Atomicity still cannot guard against concurrent, non-atomic WriteProcessMemory changes, which the post describes as already broken and outside supported hot-patching use. ### Source excerpt Suspending all the threads stops the threads that are there now, those are not the only possible sources of change. The post Why are we all worked up about atomicity when applying hot-patches if we can just suspend all the threads? appeared first on The Old New Thing. ## Linux x86 32-bit Patches Clean Old Kernel Code After Recently Removing Vintage CPUs DevFeed: [Linux x86 32-bit Patches Clean Old Kernel Code After Recently Removing Vintage CPUs]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-11-06T14:11:31Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux](), [x86](), [patches]() Tags: [32-bit](), [amd](), [cache](), [can](), [code](), [compare](), [counter](), [cpu](), [cpus](), [dependencies](), [desktop-linux](), [developer](), [exchange](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [other](), [patches](), [phoronix](), [phoronix-test-suite](), [support](), [ubuntu-benchmarks](), [ubuntu-hardware](), [vintage](), [with](), [x86]() ### AI overview After older 32-bit CPUs were removed from Linux support, Arnd Bergmann proposed x86 32-bit cleanup patches. They remove lingering AMD Elan code and other obsolete dependencies, make Time Stamp Counter (TSC) and CX8 support unconditional, require at least 64-byte cache lines, and simplify instruction-set selection. The stated aim is to remove unnecessary code and bring 32-bit x86 code closer to x86_64; the excerpt describes a patch series, not whether it was merged. ### Source excerpt With the Linux kernek having phased out i486 CPU support and dropping old AMD Elan SoC code along with removing other obsolete and stagnate 32-bit x86 hardware support, some x86 32-bit clean-ups are proceeding along with being able to make the kernel depend unconditionally now on some features... ## AMD on track to overtake Intel as biggest x86 outfit DevFeed: [AMD on track to overtake Intel as biggest x86 outfit]() Original publisher: [Read original article]() Author: Anne Barela Published: 2026-11-04T16:04:46Z Content type: news Language: en Sources: [Adafruit Industries]() Topics: [x86](), [intel]() Tags: [2026](), [advanced-packaging](), [amd](), [ceo](), [client](), [computers](), [cpu](), [data-center](), [gaming](), [growth](), [history](), [intel](), [lisa-su](), [memory](), [microprocessors](), [q3](), [results](), [revenue](), [x86]() ### AI overview AMD expects to surpass Intel in chip sales next quarter, with guidance of about $17 billion in revenue versus Intel's $15 billion to $16 billion. Its Q3 revenue rose 45 percent year over year to $13.4 billion, led by Data Center, up 97 percent to $8.5 billion. Client and gaming revenue fell 8 percent, although PC chip sales within it rose 7 percent to $2.9 billion. CEO Lisa Su forecast more than 80 percent company growth in 2027 and roughly doubled data center CPU business, saying AMD had secured the wafers, substrates, advanced packaging and memory needed. Intel would still have higher total revenue because of its foundry business. ### Source excerpt Simon Sharwood, writing for The Register, reports that AMD expects to bring in more revenue than Intel next quarter. That would make AMD the biggest vendor whose main product is the x86 processor, after years of trailing its rival. AMD's Q3 2026 results showed revenue up 45 percent year over year to $13.4 billion, with [...] ## AMD Q3 2026 Earnings Data Center Growth Drives Record Quarter DevFeed: [AMD Q3 2026 Earnings Data Center Growth Drives Record Quarter]() Original publisher: [Read original article]() Author: Cliff Robinson Published: 2026-11-04T05:24:08Z Content type: article Language: en Sources: [ServeTheHome]() Topics: [AI Infrastructure](), [x86](), [ddr5]() Tags: [2026](), [acceleration](), [aerospace](), [ai](), [ai-infrastructure](), [amd](), [anthropic](), [data-center](), [data-center-growth](), [data-center-revenue](), [defense](), [demand](), [earnings](), [embedded](), [growth](), [leadership](), [news](), [q3](), [q3-2026-earnings](), [venice](), [x86]() ### AI overview AMD reported Q3 2026 revenue of $13.377 billion, up 45% year over year, with Data Center revenue nearly doubling to $8.546 billion. AMD attributes the segment's growth to strong EPYC demand and the launch of Instinct MI450 GPUs; it says major clients are running workloads on Helios rack-scale systems. The article compares AMD's Data Center growth of 97% with Intel's 78% on $7.3 billion in quarterly revenue. Client and Gaming revenue fell 8% to $3.722 billion, while Embedded rose 29% to $1.109 billion. AMD forecast Q4 revenue of about $17 billion, plus or minus 3%, implying roughly 66% year-over-year growth at the midpoint. The article's expectations about Venice's future x86 performance leadership and Intel's Diamond Rapids timing are projections, not reported results. ### Source excerpt AMD Q3 2026 earnings were massive with the data center and embedded segments seeing big uplift with the clear Venice x86 leadership looming The post AMD Q3 2026 Earnings Data Center Growth Drives Record Quarter appeared first on ServeTheHome. ## Tor Browser 16.0 released DevFeed: [Tor Browser 16.0 released]() Original publisher: [Read original article]() Author: jzb Published: 2026-11-02T14:28:23Z Content type: release Language: en Sources: [LWN.net]() Topics: [tor](), [Firefox](), [material-you](), [User interface design]() Tags: [32-bit](), [64-bit](), [android](), [arm](), [changelog](), [design](), [esr](), [feature](), [firefox](), [generic](), [google](), [interface](), [linux](), [material-design-3](), [release](), [settings](), [tor-browser](), [version](), [window](), [x86]() ### AI overview Tor Browser 16.0 is the first stable release based on Firefox ESR 153. It adds Linux support on 64-bit Arm, redesigned settings, and generic window titles intended to make it harder for other applications to snoop on browser activity. The Android interface receives updates aligned with Google's Material Design 3. Following Firefox, the release ends support for 32-bit x86 Linux. The supplied excerpt points to the full changelog for additional updates and fixes. ### Source excerpt Version 16.0 of the Tor Browser has been released. This is the first stable version based on Firefox ESR 153. Notable changes in this release include support for Linux on 64-bit Arm, redesigned settings, and a "generic window titles" feature to help prevent other applications from snooping on one's browser activity. Tor Browser for Android has had a number of interface updates to Google's Material Design 3 design language. This release also follows Firefox in ending support for 32-bit x86 Linux systems. See the full changelog for all of the updates and bug fixes. ## I decompiled Battlefield 1942 and put it on the web with multiplayer DevFeed: [I decompiled Battlefield 1942 and put it on the web with multiplayer]() Original publisher: [Read original article]() Author: Pieter Levels Published: 2026-11-02T00:00:00Z Content type: release Language: en Sources: [@levelsio (Pieter Levels)]() Topics: [multiplayer](), [browser-game](), [Web](), [Web platform]() Tags: [ai](), [battlefield](), [demo](), [direct3d](), [doom](), [engine](), [game](), [games](), [multiplayer](), [network](), [network-stack](), [open-source](), [open-source-projects](), [opengl](), [opus-5-5](), [port](), [stuff-i-made](), [tech](), [web](), [webgl](), [websockets](), [windows](), [x86]() ### AI overview The Battlefield 1942 shareware demo was decompiled and ported to run in a web browser with multiplayer. The author says the work had no existing open source engine or prior port to build on: Claude Code disassembled roughly 57,000 x86 functions, translated them into C, and produced about 100,000 lines, which were compiled to WebAssembly with Emscripten. Around 300 Windows and Direct3D functions were rewritten to use WebGL 2 and OpenGL, and a network stack was built to connect to a multiplayer server over WebSockets. The author reports that it appears to work and invites players to report bugs. ### Source excerpt I decompiled probably my favorite game ever: Battlefield 1942 and I put it on the web with multiplayer for you to play here: 👉 bf1942.pieter.com 👈 (It's the fr... ## AMD Ryzen Zen 6 Looks Like It Will Be In Good Shape With Linux 7.4, Laptop Improvements DevFeed: [AMD Ryzen Zen 6 Looks Like It Will Be In Good Shape With Linux 7.4, Laptop Improvements]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-30T15:24:46Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux](), [x86]() Tags: [7-4](), [added](), [amd](), [amd-ryzen](), [arm](), [asus](), [battery](), [changes](), [client](), [desktop-linux](), [driver](), [improvements](), [it](), [kernel](), [laptop](), [linux](), [linux-7-4](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [platform](), [ryzen](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86](), [zen-6]() ### AI overview Linux 7.4 adds early platform-driver support for upcoming AMD Ryzen Zen 6 systems: the AMD HSMP and PMC drivers gain Zen 6 support, and the PMF driver adds the AMDI0112 ID, described as presumably for Zen 6. The excerpt also lists hardware and control support across laptop vendors, including Acer hardware monitoring, fan and battery controls; additional Alienware, MSI, HP, ASUS and Uniwill device support; and Ayaneo and OneXPlayer handhelds. Snapdragon X laptop changes include ASUS Glymur EC support and a Lenovo Yoga Slim 7x Gen 11 EC driver. These are driver additions and IDs; the excerpt does not establish broader compatibility or describe testing outcomes. ### Source excerpt The x86 platform driver changes were merged this week to the Linux 7.4 kernel ahead of the merge window closing this weekend... ## How BMW Group accelerated connected vehicle workloads on AWS Graviton DevFeed: [How BMW Group accelerated connected vehicle workloads on AWS Graviton]() Original publisher: [Read original article]() Author: Tomislav Lozančić Published: 2026-10-29T20:11:14Z Content type: article Language: en Sources: [AWS Architecture Blog]() Topics: [Graviton](), [CI/CD](), [Amazon Elastic Kubernetes Service]() Tags: [actions](), [adoption](), [advanced-300](), [amazon-ec2](), [amazon-eks](), [amazon-elastic-kubernetes-service](), [applications](), [architecture](), [automotive](), [aws](), [aws-graviton](), [bmw](), [ci-cd](), [container](), [cpu](), [customer-solutions](), [disruption](), [graviton](), [ingress](), [karpenter](), [nginx](), [performance](), [platform](), [x86]() ### AI overview BMW Group migrated its Connected Vehicle platform from x86 to AWS Graviton incrementally, while keeping both architectures available and deployments uninterrupted. Karpenter replaced fixed node groups with dynamic provisioning; tainted Graviton node pools required workloads to opt in, and dual-architecture container images let one tag serve arm64 and amd64. For image builds, native architecture-specific runners avoid QEMU emulation overhead and surface compatibility issues earlier, but require dedicated runners; QEMU builds run from one machine but can be much slower for compute-heavy workloads. BMW supported both approaches and used native Graviton runners for platform-scale arm64 builds. The article reports about $600,000 in annualized infrastructure savings, around 57% lower CPU use for the NGINX ingress controller at the same ingress profile, and about 40% better price-performance. More than 65% of the platform now runs on Graviton in production. ### Source excerpt Learn how BMW Group migrated its connected vehicle platform from x86 to AWS Graviton. Using Karpenter, multi-architecture container builds, and Graviton-based CI/CD runners, the team moved workloads without disruption, cutting NGINX ingress CPU by about 57 percent and delivering about 40 percent better price-performance. ## Quantized Edge Inference of a Self-Supervised SAR-Optical Encoder on Commodity x86 Hardware DevFeed: [Quantized Edge Inference of a Self-Supervised SAR-Optical Encoder on Commodity x86 Hardware]() Original publisher: [Read original article]() Author: Christian Sanchez-Leon, Dongming Chen Published: 2026-10-28T04:00:00Z Content type: news Language: en Sources: [arXiv: Machine Learning]() Topics: [quantization](), [x86](), [On-device AI](), [Sustainable Computing](), [AI Infrastructure]() Tags: [autoencoder](), [avx2](), [cost](), [cpu](), [cs-cv](), [cs-lg](), [deploy](), [device](), [earth](), [edge](), [edge-inference](), [eess-iv](), [energy](), [gpu](), [hardware](), [inference](), [int8](), [latency](), [linear](), [low-power](), [node](), [optical](), [x86]() ### AI overview On three commodity x86 nodes, INT8 inference of a pretrained SAR-optical masked-autoencoder encoder reduced CPU cost while preserving linear-probe accuracy: micro-mAP changed by only +0.0006, within seed spread. INT8 lowered CPU latency on every node, including a 1.45x gain on the CPU without AVX2, and reduced CPU energy wherever measured; the AVX2+VNNI reference showed a 1.53x latency gain. The best device depended on the CPU: the integrated GPU was 4.38x faster on the weakest node, while the Pareto-optimal choice shifted to the CPU as CPU capability improved. The excerpt describes measurements at FP32, FP16, and INT8, but does not provide full methods or results. ### Source excerpt arXiv:2610.37056v1 Announce Type: cross Abstract: Self-supervised vision transformers are increasingly used as reusable encoders for Earth observation, but their inference cost on the hardware available in the field is rarely characterized. We deploy a pretrained SAR-optical masked-autoencoder encoder on three commodity x86 nodes, from a low-power CPU without AVX2 to an AVX2+VNNI reference, at FP32, FP16 and INT8 on the CPU and, where present, the integrated GPU, and report latency, energy (RAPL and wall plug) and linear-probe accuracy. Quantization is accuracy-neutral: INT8 changes micro-mAP by only +0.0006, within the seed spread, so precision becomes a pure cost decision. INT8 lowers CPU latency on every node, by 1.45x even on the CPU without AVX2, and CPU energy wherever it is measured, and the VNNI reference (1.53x) suggests a further gain beyond AVX2. The Pareto-optimal device shifts from the integrated GPU, which is 4.38x faster than the CPU on the weakest node, to the CPU as the CPU class improves. ## Windows is preparing for Intel's biggest x86 change in years, but only Xeon chips will use it at first DevFeed: [Windows is preparing for Intel's biggest x86 change in years, but only Xeon chips will use it at first]() Original publisher: [Read original article]() Author: Alfonso Maruccia Published: 2026-10-26T19:06:00Z Content type: news Language: en Sources: [TechSpot]() Topics: [Windows](), [x86](), [intel](), [Xeon 600]() Tags: [advanced](), [but](), [change](), [changes](), [cpu](), [enthusiast](), [extensions](), [first](), [future](), [hardware](), [insider](), [intel](), [microsoft](), [offer](), [option](), [os](), [performance](), [releases](), [software](), [windows](), [windows-11](), [windows-insider](), [x86](), [xeon]() ### AI overview Windows Insider build 29695 contains a manually enabled APX setting that requires a reboot, but Xeno says it is currently for developers and has no practical effect on the OS. APX doubles x86-64 general-purpose registers from 16 to 32; Intel says APX-compiled code has 10% fewer loads and over 20% fewer stores than its baseline, and developers can adopt it by recompiling. Those figures suggest potential performance and dynamic-power benefits, but actual gains depend on software and workload and remain unproven. Initial compatible processors are expected to be Diamond Rapids Xeon chips; the excerpt suggests Windows support could arrive in a 2027 update. ### Source excerpt Windows enthusiast Xeno recently uncovered what could be one of the most interesting changes coming to future Windows releases. Microsoft's OS may soon offer an option to enable Advanced Performance Extensions (APX) support on compatible hardware, the self-described "Windows Insider since day one" said. In turn, APX could deliver a... Read Entire Article ## Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads DevFeed: [Toward Open ISA Supercomputing: A Comparative Study of RISC-V, Arm, and x86 Architectures on HPC Workloads]() Original publisher: [Read original article]() Author: Emanuele Venieri, Giacomo Madella, Gabriele Ceccolini, Simone Manoni, Federico Ficarelli, Filippo Barbari, Jenny Lynn Almerol, Elisabetta Boella, Nitin Shukla, Simone Bn\\\`a, Luca Benini, Andrea bartol Published: 2026-10-26T04:00:00Z Content type: comparison Language: en Sources: [arXiv: Distributed Computing]() Topics: [High-Performance Computing](), [RISC-V](), [Arm](), [x86](), [Supercomputing]() Tags: [applications](), [arm](), [bandwidth](), [benchmarks](), [cache](), [compare](), [competition](), [cs-ar](), [cs-dc](), [cs-pf](), [efficiency](), [energy-efficiency](), [evaluation](), [grace-cpu](), [hardware](), [high-performance](), [high-performance-computing](), [high-performance-computing-hpc](), [hpc](), [intel](), [risc-v](), [supercomputing](), [x86]() ### AI overview Using a common software stack and methodology, the study compares the Sophgo SG2044 RISC-V processor with NVIDIA Grace and Intel Xeon Platinum 8480+ on four HPC benchmarks and four applications. The SG2044 reaches 8.02 GFLOP/s FP64 and 7.8 GB/s memory bandwidth per core, scaling to 294 GFLOP/s and 107 GB/s at 64 cores. L2-aware placement gives near-linear scaling through 16 cores; memory-bandwidth saturation limits further gains. Its absolute performance is 8-15x lower than the Arm and x86 systems, but it has competitive scaling and energy efficiency on several workloads. For LLM decode, 64-core SG2044 execution has the strongest relative scaling and energy efficiency among the evaluated platforms and exceeds Intel in throughput. The abstract also reports substantial gains across Monte Cimone RISC-V generations. An OpenBLAS-linked HPL-MxP version used in the work is released as open source. ### Source excerpt arXiv:2610.32632v1 Announce Type: new Abstract: RISC-V is emerging as a candidate architecture for high-performance computing (HPC), but its competitiveness against established x86 and Arm processors remains difficult to assess because existing studies use different platforms, workloads, and methodologies, and rarely consider energy efficiency. Our work provides an evaluation of contemporary HPC RISC-V, Arm, and x86 processors using a common software stack and methodology. We characterize the Sophgo SG2044 and compare it with the NVIDIA Grace CPU Superchip and Intel Xeon Platinum 8480+ across four HPC benchmarks (STREAM, HPL, HPL-MxP, and HPCG) and four representative applications (iPIC3D, PLUTO, OpenFOAM, and llama.cpp). The version of HPL-MxP linked to OpenBLAS built and used for this work is made available as open-source software. The SG2044 reaches 8.02 GFLOP/s of FP64 performance and 7.8 GB/s of memory bandwidth per core, increasing to 294 GFLOP/s and 107 GB/s at 64 cores. L2-cache-aware process placement enables near-linear scaling up to 16 cores, beyond which memory-bandwidth saturation limits further gains. Across generations of RISC-V hardware, in the context of the Monte Cimone (MC) project, the SG2044-based MCv3 doubles both single-core performance and peak memory bandwidth relative to MCv2, while improving memory bandwidth, node-level FP64 performance, and energy efficiency by approximately 100x, 158x, and 10x, over MCv1. Against the Arm and x86 systems, the SG2044 shows 8-15x less absolute performance, reflecting its narrower vector resources and less advanced technology node, but delivers competitive scaling and energy efficiency on several workloads. Its most notable result is LLM decode, where 64-core execution provides the highest relative scaling and energy efficiency among the evaluated platforms while exceeding Intel in throughput. Our results show that RISC-V processors are closing the gap with the competition. ## AMD and Intel Make oneDNN the Default x86 Path in PyTorch, Folding ZenDNN In and Lining Up AI Compute Extensions DevFeed: [AMD and Intel Make oneDNN the Default x86 Path in PyTorch, Folding ZenDNN In and Lining Up AI Compute Extensions]() Original publisher: [Read original article]() Author: Harold Fritts Published: 2026-10-22T16:44:09Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [PyTorch](), [x86](), [intel](), [Open Source](), [AI Infrastructure]() Tags: [accelerate](), [advisory-group](), [ai-compute](), [amd](), [announcement](), [collaboration](), [compute-density](), [cpu](), [cpu-optimization](), [deep-learning](), [enterprise](), [epyc](), [extensions](), [intel](), [library](), [open-source](), [optimization](), [optimizations](), [pytorch](), [software](), [x86]() ### AI overview AMD and Intel are consolidating their PyTorch CPU optimizations for x86 in oneDNN, which they identify as PyTorch's default open-source x86 acceleration library. AMD is folding ZenDNN's EPYC-tuned primitives into oneDNN while continuing processor-specific optimization, aiming to put both vendors' kernels behind the same PyTorch calls and simplify access to optimized inference and training. They also plan to expose jointly defined AI Compute Extensions (ACE) through future oneDNN updates. The excerpt describes ACE's matrix instructions and supported data types, but says neither the consolidated implementation's release timeline or performance nor the processor generations that will support ACE have been announced; the claimed 16x compute density is from the ACE specification. ### Source excerpt AMD and Intel announced that they will combine their x86 CPU optimization work for PyTorch in oneDNN, the open-source deep learning library governed by the Unified Acceleration Foundation (UXL), and have aligned on it as the default open-source library for x86 acceleration inside PyTorch. AMD is folding its ZenDNN optimizations into oneDNN and has joined The post AMD and Intel Make oneDNN the Default x86 Path in PyTorch, Folding ZenDNN In and Lining Up AI Compute Extensions appeared first on StorageReview.com. ## x86 Kernel Shadow Stacks Being Worked On For Linux As Powerful Control Flow Protection DevFeed: [x86 Kernel Shadow Stacks Being Worked On For Linux As Powerful Control Flow Protection]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-22T13:22:56Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux](), [Kernel](), [x86](), [eBPF]() Tags: [about](), [all](), [also](), [amd](), [but](), [code](), [control](), [cpu](), [cpus](), [dave](), [desktop-linux](), [flow](), [intel](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [powerful](), [protection](), [return](), [stack](), [support](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86]() ### AI overview An RFC from Intel engineer Dave Hansen proposes running the Linux kernel with x86 shadow stacks, a protected parallel stack for return addresses intended to help defend against control-flow attacks. The proposal is proof of concept and seeks discussion about what an initial merge could include; Hansen says parts may be reusable while others need substantial rework. The current RFC requires Flexible Return Event Delivery (FRED), limiting support to Intel Panther Lake and newer or AMD Zen 6 and beyond. It is incompatible with several features, including Retpolines, function graph tracing, BPF trampolines, Kexec, EFI mixed mode, KVM, and Xen PV. Initial testing has been done on Intel Panther Lake. ### Source excerpt Linux user-space for several years had shadow stack support for hardware-enforced control-flow enforcement in defending against return oriented programming (ROP) attacks. Intel Tigerlake and newer CPUs or AMD Zen 3 and newer have the necessary hardware shadow stacks support. Shadow stacks have been effective for helping user-space software fend ROP attacks while now there is new work toward bringing shadow stack support for kernel space on Linux... ## Linux 7.4 Adapts AMD Zen 6 For Less Costly CPU Security Mitigation DevFeed: [Linux 7.4 Adapts AMD Zen 6 For Less Costly CPU Security Mitigation]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-22T09:40:39Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux](), [Security]() Tags: [7-4](), [also](), [amd](), [behavior](), [benchmarks](), [better](), [branch](), [bugs](), [cpu](), [desktop-linux](), [kernel](), [less](), [linux](), [linux-7-4](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [processors](), [pull-request](), [request](), [security](), [this](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86](), [zen-6]() ### AI overview For AMD Zen 6, Linux 7.4 uses the processor's per-context BTB tagging to isolate branch targets across contexts, allowing the more costly SRSO SafeRET mitigation to be disabled. The x86/bugs change detects and handles this capability; it also fixes Spectre v2 mitigation reporting for RETPOLINE=n builds. The excerpt says backports to earlier stable kernels and performance benchmark results remain to be seen. ### Source excerpt The x86/bugs pull request was merged this week for the Linux 7.4 kernel. Most notable here is adjusting the CPU security mitigations for AMD Zen 6 processors... ## Linus Torvalds Eliminates Unsafe \_\_get\_user() & \_\_put\_user() Functions In Linux 7.4 DevFeed: [Linus Torvalds Eliminates Unsafe \_\_get\_user() & \_\_put\_user() Functions In Linux 7.4]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-21T21:11:58Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux](), [Claude Code](), [generative-ai-tools]() Tags: [7-4](), [ai](), [ai-coding](), [architecture](), [arm64](), [claude](), [claude-code](), [cpu](), [desktop-linux](), [functions](), [git](), [git-merge](), [kernel](), [linus-torvalds](), [linux](), [linux-7-4](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-kernel](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [safety](), [static-analysis](), [ubuntu-benchmarks](), [ubuntu-hardware](), [validation](), [x86]() ### AI overview Linux 7.4 removes the historical __get_user() and __put_user() functions from generic kernel code and completes their removal on x86/x86_64. These faster variants lacked user-address range checks, which Torvalds says made misuse insecure and often slower than using the proper interfaces. Most call sites had already been converted; scoped user access region helpers make modern interfaces easier to use. Some architecture ports retain remnants for non-trivial cases, while ARM64 maps these functions to get_user() and put_user(). Torvalds also said he used Claude as a kind of Coccinelle script for the removal. ### Source excerpt Linus Torvalds continues with his recent uptick in kernel patches himself, assisted in part by AI with Claude Code. Merged today was removing the historical and unsafe __get_user() and __put_user() kernel functions... ## Linux 7.4 Kernel Crypto Library Enjoying Optimized AES Implementations On x86 & RISC-V DevFeed: [Linux 7.4 Kernel Crypto Library Enjoying Optimized AES Implementations On x86 & RISC-V]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-21T20:11:03Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux](), [x86](), [Library](), [RISC-V]() Tags: [2026](), [7-4](), [accelerated](), [acceleration](), [aes](), [crypto](), [cryptographic](), [desktop-linux](), [engineer](), [faster](), [google](), [kernel](), [library](), [linux](), [linux-7-4](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-kernel](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [optimized](), [performance](), [phoronix](), [phoronix-test-suite](), [risc-v](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86](), [x86-64]() ### AI overview Merged for Linux 7.4, optimized AES implementations for ECB, CBC, CBC-CTS, CTR, XCTR and XTS were moved into the kernel crypto library for x86/x86_64 and RISC-V. This accelerates the library APIs on those architectures while preserving acceleration for crypto_skcipher; x86_64 uses AVX-optimized code and AES-NI. The change also removes duplicated glue code. Separately, SPARC64 gains an optimized AES-XTS implementation using its crypto opcodes. ### Source excerpt The latest Linux kernel cryptographic subsystem performance work carried out by Google engineer Eric Biggers is migrating x86/x86_64 and RISC-V optimized implementations of different AES modes into the lib/crypto kernel crypto library to enjoy faster performance there... ## Accelerating HQC for Post-Quantum TLS 1.3 on x86 IoT Gateways DevFeed: [Accelerating HQC for Post-Quantum TLS 1.3 on x86 IoT Gateways]() Original publisher: [Read original article]() Author: Jihoon Jang, Hyunju Park, Jebin Kim, Seokhie Hong, Suhri Kim Published: 2026-10-21T04:00:00Z Content type: article Language: en Sources: [arXiv: Cryptography and Security]() Topics: [Post-quantum cryptography](), [TLS (Transport Layer Security)](), [TLS handshake](), [x86](), [Latency](), [Internet of things]() Tags: [avx2](), [bandwidth](), [client](), [cpu](), [cs-cr](), [decoding](), [generation](), [handshake](), [implementation](), [integrate](), [intel](), [intel-core](), [iot](), [latency](), [ml](), [ml-kem](), [network](), [post-quantum](), [tls](), [tls-1-3](), [x86]() ### AI overview The work optimizes HQC on x86 using AVX2, AVX-512, and GFNI, then integrates the implementations into TLS 1.3. Changes include faster polynomial multiplication, Reed-Solomon and Reed-Muller decoding, SHA3-512, and fixed-weight sampling; HQC-5 also uses FAFFT multiplication with AVX-512 and GFNI. On an Intel Core i5-1135G7, AVX2 cuts decapsulation time by 11.1-21.5% versus prior AVX2 results. Across three parameter sets, AVX-512 improves key generation, encapsulation, and decapsulation by 24.9-29.5%, 10.4-11.1%, and 20.6-26.1%, respectively, versus Cabral et al. In loopback TLS, HQC-5 handshake latency falls from 3.22 ms to 2.92 ms. On a 1 Mbit/s path with 50 ms added RTT, however, HQC-5 takes 243 ms versus 87 ms for ML-KEM-1024, with key and ciphertext sizes driving the remaining cost on constrained links. ### Source excerpt arXiv:2610.11107v2 Announce Type: replace Abstract: Post-quantum TLS at an IoT gateway must protect many device connections without large increases in handshake delay, CPU cost, or network traffic. HQC provides code-based diversity beyond ML-KEM, but its computation and ciphertext sizes can increase these costs. We optimize HQC for x86 processors with AVX2, AVX-512, and the Galois Field New Instructions (GFNI), and integrate the resulting implementations into TLS 1.3. We extend branch-free Toom-Cook/Karatsuba multiplication to AVX-512, accelerate Reed-Solomon decoding with GFNI, improve Reed-Muller decoding, accelerate SHA3-512 and fixed-weight sampling, and port Frobenius additive FFT (FAFFT) multiplication to AVX-512 + GFNI for HQC-5. On an Intel Core i5-1135G7 processor, our AVX2 implementation reduces decapsulation by 11.1-21.5% over the fastest prior AVX2 results. Our AVX-512 implementation reduces key generation by 24.9-29.5%, encapsulation by 10.4-11.1%, and decapsulation by 20.6-26.1% relative to Cabral et al. across the three HQC parameter sets. We evaluate the effects of these implementations on TLS 1.3 handshake latency and server and client CPU costs, as well as the effects of round-trip time (RTT) and bandwidth. In local loopback TLS measurements, our AVX-512 HQC-5 implementation reduces handshake latency from 3.22 ms to 2.92 ms compared with Cabral et al. On a constrained path with 1 Mbit/s bandwidth and an added RTT of 50 ms, the HQC-5 handshake takes 243 ms, compared with 87 ms for ML-KEM-1024. This indicates that HQC public-key and ciphertext sizes, rather than implementation speed, determine the remaining handshake cost on constrained links. ## Intel & AMD Now Collaborating On Software Optimizations With PyTorch/oneDNN DevFeed: [Intel & AMD Now Collaborating On Software Optimizations With PyTorch/oneDNN]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-20T16:50:52Z Content type: news Language: en Sources: [Phoronix]() Topics: [PyTorch](), [intel](), [Open Source](), [open source communities]() Tags: [acceleration](), [amd](), [arm](), [cpu](), [desktop-linux](), [intel](), [isa](), [library](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [open-source](), [open-source-graphics](), [optimizations](), [phoronix](), [phoronix-test-suite](), [pytorch](), [qualcomm](), [samsung](), [software](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86]() ### AI overview Intel and AMD announced they will combine their x86 CPU optimization work for PyTorch through oneDNN, which they intend to focus on as PyTorch's default open-source library for x86 acceleration. AMD's ZenDNN optimizations are slated to be incorporated into oneDNN. The excerpt also says AMD will join the UXL Foundation as a steering member; it gives no further implementation details or timeline. ### Source excerpt Intel has long worked on tuning their oneDNN neural network library for their hardware and saw its adoption by PyTorch and other AI frameworks. AMD has maintained ZenDNN as their downstream fork that is oneDNN API compatible while catering to their Zen processor designs. As an interesting twist, AMD and Intel jointly announced today they will be collaborating around oneDNN for PyTorch and pushing the AMD Zen improvements into oneDNN... ## Why x86 processors still start in 16-bit real mode DevFeed: [Why x86 processors still start in 16-bit real mode]() Original publisher: [Read original article]() Author: Anne Barela Published: 2026-10-13T14:50:34Z Content type: article Language: en Sources: [Adafruit Industries]() Topics: [cpu](), [Chip design](), [Linux]() Tags: [8086](), [code](), [compatibility](), [cpu](), [history](), [intel](), [kernel](), [linux](), [microprocessors](), [operating-system](), [qemu](), [real-mode](), [uefi](), [windows-11](), [x86]() ### AI overview x86 processors begin execution in 16-bit real mode, a startup state inherited from the Intel 8086. Firmware quickly switches to protected mode, but additional CPU cores repeat the process, and operating systems retain startup stubs for it. Intel abandoned its 2023 proposal to start directly in 64-bit mode; a possible alternative was later discussed, though the processor described was unnamed. ### Source excerpt Adam Conway, writing at XDA Developers, lays out how every x86 processor still starts in real mode, the 16-bit execution environment of the Intel 8086 from June 1978. Intel's documentation says its 64-bit designs come out of reset in the same state as the original 8086, and AMD says its chips always enter real mode [...] ## Graft: replace dependencies CLI DevFeed: [Graft: replace dependencies CLI]() Original publisher: [Read original article]() Author: tomberek Published: 2026-10-13T02:16:04Z Content type: article Language: en Sources: [Announcements - NixOS Discourse]() Topics: [NixOS](), [cURL]() Tags: [announcements](), [cli](), [linux](), [nix](), [nixos](), [nixpkgs](), [openssl](), [x86](), [x86-64]() ### AI overview Graft is a command-line tool for replacing dependencies in Nix store paths without reevaluating Nix expressions. The discussion demonstrates swapping curl's OpenSSL dependency and editing generated NixOS configuration, while warning that grafting libraries can cause compatibility failures. ### Source excerpt (claude was used... extensively) Graft replaces dependencies at the store layer, bypassing the normal Nix eval. Inspired by Guix graft. While we do have replaceDependency and system.replaceDependencies I thought it would be nice to have a Guix-style CLI to run grafts more manually and without having to re-evaluate Nix expressions that you may/may-not still have around. Eg: $ nix run nixpkgs/nixos-25.11#curl -- --version curl 8.20.0 (x86_64-pc-linux-gnu) libcurl/8.20.0 OpenSSL/3.6.2 ... $ export curl="$(nix eval nixpkgs/nixos-25.11#curl.outPath --raw)" $ graft replace $curl --override-name openssl nixpkgs/nixos-26.05#openssl.out ... grafted /nix/store/r4p5r6q0n3lmidd0yq2zblqxvim0xsb3-krb5-1.22.1-lib -> /nix/store/nxa80mkh75x6cik14mqcbd0d34b3c1nz-krb5-1.22.1-lib grafted /nix/store/rngyrpv421p1cnn78d5ph2y5ylg133n7-curl-8.20.0 -> /nix/store/qap31yikgr3hadwg455pl96k8rs2bbjn-curl-8.20.0 grafted /nix/store/2nmfyy3jjgn2m8d1p7lwbbxakl4ciwfc-curl-8.20.0-bin -> /nix/store/yklqiif3wxlh67sidmaflv7il2dykmn6-curl-8.20.0-bin 5 grafted, 1 explicit replacement, 15 unchanged (21 total) /nix/store/yklqiif3wxlh67sidmaflv7il2dykmn6-curl-8.20.0-bin $ /nix/store/yklqiif3wxlh67sidmaflv7il2dykmn6-curl-8.20.0-bin/bin/curl --version curl 8.20.0 (x86_64-pc-linux-gnu) libcurl/8.20.0 OpenSSL/3.6.5 ... $ nix path-info -r /nix/store/yklqiif3wxlh67sidmaflv7il2dykmn6-curl-8.20.0-bin | grep openssl /nix/store/kysvfcf8d8v26rr32xfqji8ri2lczlqk-openssl-3.6.5 Can this be very unsafe? YES! The tool is sharp. Beware the "Segmentation fault" and "version `GLIBC_2.43' not found" when messing with libraries. Probably safer to be replacing full executable binaries. Is this actually useful? Not sure, but there are some cases this can be useful. Let's say I want to quickly test out an edit to a config file that I just can't de-tangle from a convoluted NixOS module or I don't have the Nix expressions for: $ export EDITOR=vim $ head /etc/nix/nix.conf # WARNING: this file is generated from the nix.* options in # your ## Python 3.15 Released With Experimental JIT Compiler Running Faster DevFeed: [Python 3.15 Released With Experimental JIT Compiler Running Faster]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-09T14:58:00Z Content type: news Language: en Sources: [Phoronix]() Topics: [Python](), [Numba]() Tags: [c](), [compiler](), [configuration](), [desktop-linux](), [faster](), [interpreter](), [jit](), [library](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [macos](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [programming](), [programming-language](), [python-3-15](), [python-programming](), [release](), [standard-library](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86](), [x86-64]() ### AI overview Python 3.15 is described as introducing an experimental JIT compiler that is faster than the standard interpreter in cited benchmarks. The release also adds language and standard library changes, C API improvements, and default frame pointers for observability. ### Source excerpt Python 3.15 is out today as the newest annual feature release for the Python programming language... ## Patches Updated To Begin Removing The Linux x32 ABI DevFeed: [Patches Updated To Begin Removing The Linux x32 ABI]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-08T12:09:53Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux Kernel](), [Linux]() Tags: [adoption](), [amd](), [attack-surface](), [desktop-linux](), [i386](), [intel](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [lts](), [open-source-graphics](), [patches](), [phoronix](), [phoronix-test-suite](), [retirement](), [ubuntu-benchmarks](), [ubuntu-hardware](), [x86](), [x86-64]() ### AI overview Linux kernel developers have proposed patches to begin removing the x32 ABI by marking it as BROKEN. The proposal cites limited adoption and security concerns; removal would follow after this year's last LTS kernel. ### Source excerpt Linux developers are once again considering the removal of the Linux x32 ABI... ## Kage: Google Experimenting With Linux Driver Isolation Using In-Kernel LFI Sandboxes DevFeed: [Kage: Google Experimenting With Linux Driver Isolation Using In-Kernel LFI Sandboxes]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-10-07T12:50:16Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux](), [Linux Kernel](), [IPython]() Tags: [desktop-linux](), [driver](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-performance](), [linux-server-benchmarks](), [llvm](), [network](), [nvme](), [open-source-graphics](), [phoronix](), [phoronix-test-suite](), [sandboxes](), [stanford](), [technology](), [ubuntu-benchmarks](), [ubuntu-hardware](), [virtio](), [wifi](), [x86](), [x86-64]() ### AI overview Google engineers are developing Kage, a Linux kernel subsystem that isolates device drivers in in-kernel sandboxes using LLVM's Lightweight Fault Isolation. Prototypes have run NVMe, network, and Wi-Fi drivers in sandboxed environments; further performance testing is needed, and GPU driver sandboxing remains under exploration. Google may consider Kage for Android device drivers. ### Source excerpt Google engineers are experimenting with Linux kernel device driver isolation using in-kernel sandboxes leveraging LLVM's Lightweight Fault Isolation (LFI) functionality... ## Why does the compiler sometimes use ud2 and sometimes int 3 for code that shouldn't execute? DevFeed: [Why does the compiler sometimes use ud2 and sometimes int 3 for code that shouldn't execute?]() Original publisher: [Read original article]() Author: Raymond Chen Published: 2026-10-06T14:00:00Z Content type: article Language: en Sources: [Raymond Chen]() Topics: [Compiler](), [conditionals]() Tags: [breakpoint](), [code](), [compilers](), [old-new-thing](), [undefined-behavior](), [x86]() ### AI overview The article explains why x86 compilers use the one-byte int 3 instruction for padding where execution should never reach, and ud2 to mark code paths that should be unreachable because of undefined behavior. It suggests investigating logic flaws after ud2, and invalid or uninitialized function pointers or breakpoints after int 3. ### Source excerpt It shouldn't execute, but for different reasons. The post Why does the compiler sometimes use ud2 and sometimes int 3 for code that shouldn't execute? appeared first on The Old New Thing. [Next page]()