# XOR Published articles for XOR. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Linux 7.4 slated to merge AVX-512 optimization for xor\_gen() DevFeed: [Linux 7.4 slated to merge AVX-512 optimization for xor\_gen()]() Original publisher: [Read original article]() Author: Michael Larabel Published: 2026-09-16T00:53:15Z Content type: news Language: en Sources: [Phoronix]() Topics: [Linux](), [Kernel](), [patches](), [Code](), [cpu](), [intel](), [Google]() Tags: [amd](), [cpu](), [desktop-linux](), [google](), [intel](), [kernel](), [linux](), [linux-benchmarking](), [linux-hardware-benchmarks](), [linux-hardware-reviews](), [linux-how-to](), [linux-kernel](), [linux-performance](), [linux-server-benchmarks](), [open-source-graphics](), [patches](), [phoronix](), [phoronix-test-suite](), [server-cpus](), [ubuntu-benchmarks](), [ubuntu-hardware](), [xor]() ### AI overview Linux 7.4 is slated to merge an AVX-512 optimization for xor_gen(), a function used by Linux software RAID to generate and validate parity blocks for RAID5 and RAID6. The patches report performance gains on AMD Zen 4 and newer CPUs and current Intel server CPUs with AVX-512, subject to final merge-window changes. ### Source excerpt Over the past few months there have been patches floating around for an AVX-512 optimized xor_gen() for the Linux kernel for that functuon used by the Linux software RAID code. It's been shhowing very nice performance gains with this function being used for generating and validating parity blocks such as for RAID5 and RAID6. The upcoming Linux 7.4 cycle is slated to merge this nice enhancement for benefiting AMD Zen 4 and newer or current Intel server CPUs with AVX-512... ## The Permanent Threat: Analyzing Aeternum's Blockchain-Based C2 Operations and Communications DevFeed: [The Permanent Threat: Analyzing Aeternum's Blockchain-Based C2 Operations and Communications]() Original publisher: [Read original article]() Author: Chris Navarrete, Sai Sathvik Ruppa and Haozhe Zhang Published: 2026-08-10T22:00:02Z Content type: article Language: en Sources: [Unit 42]() Topics: [Aeternum](), [C++](), [Firewall]() Tags: [aeternum](), [analysis](), [blockchain](), [c-plus-plus](), [c2](), [infection-chain](), [json](), [malware](), [python](), [rpc](), [telegram](), [threat-research](), [xmrig](), [xor]() ### AI overview An analysis of the Aeternum botnet loader, which uses Polygon blockchain smart contracts and public RPC endpoints for decentralized command-and-control. It also examines related Python malware using the Telegram API and a blended threat involving XWorm RAT, XMRig, and data exfiltration. ### Source excerpt Analysis of the Aeternum botnet loader, a threat leveraging Polygon blockchain smart contracts for decentralized C2 infrastructure and payload execution. The post The Permanent Threat: Analyzing Aeternum's Blockchain-Based C2 Operations and Communications appeared first on Unit 42. ## Cracking simple XOR cipher with simulated annealing, part II DevFeed: [Cracking simple XOR cipher with simulated annealing, part II]() Original publisher: [Read original article]() Published: 2026-06-21T22:00:00Z Content type: tutorial Language: en Sources: [Dennis Yurichev]() Topics: [Encryption](), [Cryptography](), [Script]() Tags: [encryption](), [script](), [video](), [xor]() ### AI overview A technical blog post describes using simulated annealing to crack a simple XOR cipher found in NetHack's nhdat file. The author identifies a repeating five-character pattern, finds the XOR key, and confirms that the decrypted result is English text. ### Source excerpt Cracking simple XOR cipher with simulated annealing, part II ## Socks, a matching game based on an additive combinatorics problem DevFeed: [Socks, a matching game based on an additive combinatorics problem]() Original publisher: [Read original article]() Published: 2023-10-14T06:00:00Z Content type: article Language: en Sources: [Jeremy Kun]() Topics: [math](), [structure]() Tags: [additive-combinatorics](), [board-games](), [card-game](), [combinatorics](), [game](), [games](), [group-theory](), [math](), [mathematics](), [structure](), [xor]() ### AI overview This article introduces Socks, a matching game modeled using six-dimensional binary vectors and additive combinatorics. It proves that any seven cards contain a valid zero-summing set, while six specific cards can avoid one, so the minimum guarantee is seven cards. ### Source excerpt Can you find a set of cards among these six, such that the socks on the chosen cards can be grouped into matching pairs? (Duplicate pairs of the same sock are OK) Spoilers: If the cards are indexed as 1 2 3 4 5 6 Then the following three subsets work: $\{ 1, 2, 4, 5, 6 \}$, $\{ 2, 3, 6 \}$, and $\{ 1, 3, 4, 5 \}$. ## Authenticated encryption: why you need it and how it works DevFeed: [Authenticated encryption: why you need it and how it works]() Original publisher: [Read original article]() Author: andreacorbellini Published: 2023-03-09T18:35:00Z Content type: tutorial Language: en Sources: [Andrea Corbellini]() Topics: [Cryptography](), [Encryption](), [ChaCha](), [Algorithms]() Tags: [algorithms](), [cryptographic](), [cryptography](), [encryption](), [private-key](), [public-key](), [stream](), [xor]() ### AI overview This tutorial explains malleability in modern cryptographic ciphers and how authenticated encryption addresses it. It introduces symmetric ciphers, illustrates the issue with examples, and discusses ChaCha20-Poly1305 and AES-GCM. ### Source excerpt In this article I want to explore a common problem of modern cryptographic ciphers: malleability. I will explain that problem with some hands-on examples, and then look in detail at how that problem is solved through the use of authenticated encryption. I will describe in particular two algorithms that provide authenticated encryption: ChaCha20-Poly1305 and AES-GCM, and briefly mention some of their variants. The problem ... ## Group Actions and Hashing Unordered Multisets DevFeed: [Group Actions and Hashing Unordered Multisets]() Original publisher: [Read original article]() Published: 2021-10-14T08:00:00Z Content type: article Language: en Sources: [Jeremy Kun]() Topics: [hashing](), [Programming]() Tags: [abelian-groups](), [group-actions](), [group-theory](), [groups](), [hashing](), [mathematics](), [multiset](), [multisets](), [practical](), [programming](), [xor]() ### AI overview The article introduces a result by Kevin Ventullo that applies group actions to hash functions for unordered sets and multisets. It explains why incremental, order-independent hashing is useful and describes collision-related weaknesses of addition and XOR approaches. ### Source excerpt I learned of a neat result due to Kevin Ventullo that uses group actions to study the structure of hash functions for unordered sets and multisets. This piqued my interest because a while back a colleague asked me if I could think of any applications of "pure" group theory to practical computer programming that were not cryptographic in nature. He meant, not including rings, fields, or vector spaces whose definitions happen to be groups when you forget the extra structure. ## Boolean not DevFeed: [Boolean not]() Original publisher: [Read original article]() Published: 2020-10-31T00:00:00Z Content type: tutorial Language: en Sources: [Vasya Drobushkov]() Topics: [Kotlin](), [Code](), [Programming](), [function]() Tags: [boolean](), [kotlin](), [logic](), [operator](), [programming](), [programming-languages](), [xor]() ### AI overview This Kotlin tutorial explains Boolean negation, focusing on the not() method and the readability of different ways to express negative conditions. It recommends positive function names in general, with negative forms added when they represent common business logic, and explains that not() is an operator function. ### Source excerpt Introduction Boolean is one of the essential types in programming and probably one of the simplest because it has only two values: true and false. Boolean are usually used as flags for control flow, specifically, conditions. if (string.isEmpty()) { println("String is empty") } It is not much interesting in Boolean, but in Kotlin there is one thing which might be confusing if used - it is method not(). Negate Boolean If we look at declaration of Boolean class in Kotlin we'll see five methods, four of which are pretty obvious: and, or, xor and compareTo. And the fifth is not: ## Avoiding Vendor- and Version-Specific VM Bugs DevFeed: [Avoiding Vendor- and Version-Specific VM Bugs]() Original publisher: [Read original article]() Published: 2018-12-04T00:00:00Z Content type: article Language: en Sources: [Jake Wharton]() Topics: [Android](), [R8](), [Java](), [Code](), [cpu]() Tags: [android](), [code](), [java](), [r8](), [tool](), [xor]() ### AI overview This article examines vendor-specific and version-specific virtual machine bugs discovered while building and deploying D8. It explains how D8 converts stack-based Java bytecode into register-based Dalvik bytecode for Android, using Java's bitwise not operation as an example. The conversion uses an exclusive-or with -1 rather than a dedicated bitwise-not instruction, in part because of compatibility considerations involving the older tool. ### Source excerpt Note: This post is part of a series on D8 and R8, Android's new dexer and optimizer, respectively. For an intro to D8 read "Android's Java 8 support". The first two posts (1, 2) in this series explored how D8 is responsible for desugaring new Java language features to work on all versions of Android. Desugaring is the more interesting feature to demonstrate, but it's secondary functionality of D8. The primary responsibility is converting the stack-based Java bytecode into register-based Dalvik bytecode so that it can run on Android's VM. At this point in Android's tenure it'd be reasonable to think that this conversion (called dexing) is a solved problem. During the process of building and rolling out D8, however, interesting vendor-specific and version-specific bugs in different VMs were uncovered which this post is going to explore. Not A Not D8 takes compiled Java bytecode and produces equivalent functionality using Dalvik bytecode. We can see this with a simple example that uses Java's bitwise not operator. class Not { static void print(int value) { System.out.println(~value); } } Compiling and dumping the class file shows the bytecodes that are used to implement this feature. $ javac *.java $ javap -c *.class class Not { static void print(int); Code: 0: getstatic #2 // Field java/lang/System.out:Ljava/io/PrintStream; 3: iload_0 4: iconst_m1 5: ixor 6: invokevirtual #3 // Method java/io/PrintStream.println:(I)V 9: return } Bytecode index 3, 4, and 5 load the argument value onto the stack, load the constant -1, and perform a bitwise exclusive-or. If your bitwise skills are a little rusty, -1 is represented as all 1s and an exclusive-or sets a bit if and only if one of the two bits is set. 00010100 (value) xor 11111111 (-1) = 11101011 By performing an exclusive-or on a number whose bits are all set to 1, we are left with a number whose bits are the opposite of the original yielding the bitwise not. Running this through D8 shows the operation is implemented similar ## Obfuscated Constants DevFeed: [Obfuscated Constants]() Original publisher: [Read original article]() Author: Shai Almog Published: 2017-02-14T00:00:00Z Content type: tutorial Language: en Sources: [CodeName One]() Topics: [obfuscation](), [Reverse Engineering](), [Security](), [App](), [JavaScript]() Tags: [app](), [javascript](), [obfuscation](), [reverse-engineering](), [security](), [xor]() ### AI overview The article explains how readable string constants can help reverse-engineer an application even when method names are obfuscated. It presents simple XOR-based string obfuscation methods and an accompanying browser-based encoder, while emphasizing that obfuscation is only a temporary obstacle and that critical secrets should be stored on a server. ### Source excerpt One of the first things a hacker will do when compromising an app is look at it. E.g. if I want to exploit a bank's login UI I would look at the label next to the login and then search for it in the decompiled code. So if the UI has the String "enter user name and password" I can search for that. It won't lead directly to a hack or exploit but it will show you the approximate area of the code where we should look and it makes the first step that much easier. Obfuscation helps as it removes descriptive method names but it can't hide the Strings we use in constants. So if an app has a secret encoding it even slightly can make a difference... ## Can cached memory accesses do double-sided row hammering? DevFeed: [Can cached memory accesses do double-sided row hammering?]() Original publisher: [Read original article]() Author: Mark Seaborn (noreply@blogger.com) Published: 2015-05-11T22:35:00Z Content type: opinion Language: en Sources: [Mark Seaborn]() Topics: [Cache](), [cpu]() Tags: [cache](), [cpu](), [dram](), [mapping](), [rowhammer](), [xor]() ### AI overview This article examines whether double-sided Rowhammer attacks can be performed using cached memory accesses instead of CLFLUSH. For the author's Sandy Bridge test machine, cache-set, DRAM-bank, and row-address constraints make selecting suitable addresses impossible, leaving single-sided hammering or two sets of 13 addresses as possible approaches. ### Source excerpt There are indications that it is possible to cause bit flips in memory by row hammering without using CLFLUSH, using normal cached memory accesses. This makes me wonder: Is it possible to do double-sided row hammering using cached memory accesses, or only single-sided row hammering? The former is more likely to cause bit flips, and might be the only way to cause bit flips on some machines, such as those using a 2x refresh rate -- i.e. those configured to refresh DRAM every 32ms instead of every 64ms. (See the rowhammer blog post for more background.) The answer appears to be "no" -- at least on my test machine. For this machine (which has a Sandy Bridge CPU), I figured out how physical addresses map to cache sets and to banks and rows in DRAM. We can use these mappings to answer questions about what kinds of row hammering are possible using cached memory accesses. More specifically, my question is this: For a machine with an N-way L3 cache, is it possible to pick N+1 addresses that map to the same cache set, where at least two of these addresses map to rows R-1 and R+1 in one bank (for some neighbouring row R)? If so, repeatedly accessing these addresses would cause cache misses that cause rows R-1 and R+1 to be repeatedly activated. That puts more stress on row R (the victim row) than repeatedly activating only row R-1 or row R+1. The answer to this is "no": It's not possible to pick two such physical addresses. Here's why: Suppose we have two such addresses, A and B. Then: The addresses map to the same bank, so: (1): A[14:17] ^ A[18:21] = B[14:17] ^ B[18:21] (using the bank/row XOR scheme I described previously) The addresses are 2 rows apart, so: (2): A[18:32] + 2 = B[18:32] The addresses map to the same cache set, so: (3): A[6:17] = B[6:17] (also, SliceHash(A[17:32]) = SliceHash(B[17:32]), but we don't need this property) (2) implies that A[19] = ~B[19]. (3) implies that A[14:17] = B[14:17]. Combining that with (1) gives A[18:21] = B[18:21]. That implies A[19] = ## L3 cache mapping on Sandy Bridge CPUs DevFeed: [L3 cache mapping on Sandy Bridge CPUs]() Original publisher: [Read original article]() Author: Mark Seaborn (noreply@blogger.com) Published: 2015-04-27T21:59:00Z Content type: article Language: en Sources: [Mark Seaborn]() Topics: [Cache](), [cpu](), [intel](), [systems]() Tags: [cache](), [cpu](), [hash](), [intel](), [kernel](), [memory](), [paper](), [protocol](), [rowhammer](), [side-channel](), [slices](), [xor]() ### AI overview The article explains how physical addresses map to cache sets and slices in the L3 cache of Intel Sandy Bridge CPUs. It reports a previously published mapping for four-core CPUs and presents the author's mapping for two-core CPUs, with applications to kernel ASLR analysis and row-hammering research. ### Source excerpt In 2013, some researchers reverse-engineered how Intel Sandy Bridge CPUs map physical addresses to cache sets in the L3 cache (the last-level cache). They were interested in the cache mapping because it can be used to defeat kernel ASLR. I'm interested because the cache mapping can be used to test whether cached memory accesses can do row hammering (which can cause exploitable bit flips in some DRAM devices). The researchers published the details in the paper "Practical Timing Side Channel Attacks Against Kernel Space ASLR" (Ralf Hund, Carsten Willems and Thorsten Holz). They only published the mapping for 4-core CPUs, but I have figured out the mapping for 2-core CPUs as well. Some background: On Sandy Bridge CPUs, the L3 cache is divided into slices. Physical addresses are hashed to determine which slice of the L3 cache they will be stored in. The L3 cache is distributed and ring-based. There is one slice per core, but all the cores in a CPU can access all the cache slices via a ring bus which connects all the cores and their caches together. When a core accesses a memory location, the location will be slightly slower to access if it maps to a different core's cache slice, because it would take one or two hops around the ring bus to access it. The protocol used on the ring bus is based on QPI (Intel's QuickPath Interconnect). (QPI is a protocol used for connecting multiple CPUs together on high-end multi-socket systems.) Each cache slice contains 2048 cache sets. On lower-end CPUs, cache sets are 12-way associative, so a cache slice is 1.5MB in size (2048 sets * 12 ways * 64 bytes per cache line = 1.5MB). On higher-end CPUs, cache sets are 16-way associative, so a cache slice is 2MB in size (2048 sets * 16 ways * 64 bytes per cache line = 2MB). Cache mapping The researchers (Hund et al) figured out that the L3 cache uses the bits of a physical address as follows: Bits 0-5: These give the 6-bit byte offset within a 64-byte cache line. Bits 6-16: These give the 11-b ## You Can Do Any Kind of Atomic Read-Modify-Write Operation DevFeed: [You Can Do Any Kind of Atomic Read-Modify-Write Operation]() Original publisher: [Read original article]() Author: Jeff Preshing Published: 2015-04-02T11:20:00Z Content type: tutorial Language: en Sources: [Jeff Preshing]() Topics: [Code](), [Concurrency](), [Concurrent Programming](), [cpu]() Tags: [atomic](), [cas](), [code](), [concurrent](), [cpu](), [implementation](), [lock-free](), [shift-left](), [thread](), [xor]() ### AI overview This article explains how to implement arbitrary atomic read-modify-write operations in C++11 using compare-and-swap loops. It covers lock-free behavior, the role of CPU instructions, and the challenges of concurrent modifications. ### Source excerpt Atomic read-modify-write operations - or "RMWs" - are more sophisticated than atomic loads and stores. They let you read from a variable in shared memory and simultaneously write a different value in its place. In the C++11 atomic library, all of the following functions perform an RMW: std::atomic<>::fetch_add() std::atomic<>::fetch_sub() std::atomic<>::fetch_and() std::atomic<>::fetch_or() std::atomic<>::fetch_xor() std::atomic<>::exchange() std::atomic<>::compare_exchange_strong() std::atomic<>::compare_exchange_weak() fetch_add, for example, reads from a shared variable, adds another value to it, and writes the result back - all in one indivisible step. You can accomplish the same thing using a mutex, but a mutex-based version wouldn't be lock-free. RMW operations, on the other hand, are designed to be lock-free. They'll take advantage of lock-free CPU instructions whenever possible, such as ldrex/strex on ARMv7. A novice programmer might look at the above list of functions and ask, "Why does C++11 offer so few RMW operations? Why is there an atomic fetch_add, but no atomic fetch_multiply, no fetch_divide and no fetch_shift_left?" There are two reasons: Because there is very little need for those RMW operations in practice. Try not to get the wrong impression of how RMWs are used. You can't write safe multithreaded code by taking a single-threaded algorithm and turning each step into an RMW. Because if you do need those operations, you can easily implement them yourself. As the title says, you can do any kind of RMW operation! Compare-and-Swap: The Mother of All RMWs Out of all the available RMW operations in C++11, the only one that is absolutely essential is compare_exchange_weak. Every other RMW operation can be implemented using that one. It takes a minimum of two arguments: shared.compare_exchange_weak(T& expected, T desired, ...); This function attempts to store the desired value to shared, but only if the current value of shared matches expected. It return ## What is special about Nim? DevFeed: [What is special about Nim?]() Original publisher: [Read original article]() Published: 2014-12-31T23:00:00Z Content type: tutorial Language: en Sources: [Dennis Felsing]() Topics: [Nim](), [Programming](), [Programming language](), [Compiler](), [Tutorial]() Tags: [arrays](), [build](), [compiler](), [import](), [metaprogramming](), [nim](), [programming](), [programming-language](), [run](), [sequences](), [syntax](), [tutorial](), [xor]() ### AI overview An introductory article that demonstrates Nim through runnable examples, compile-time execution, CRC32 table generation, templates, macros, and language extension techniques. ### Source excerpt Russian Translation by frol, Chinese Translation by JiyinYiyong, Japanese Translation by Mutsuha Asada The Nim programming language is exciting. While the official tutorial is great, it slowly introduces you to the language. Instead I want to quickly show what you can do with Nim that would be more difficult or impossible in other languages. I discovered Nim in my quest to find the right tools to write a game, HookRace, the successor of my current DDNet game/mod of Teeworlds. Since I'm busy with other projects for now, this blog is now officially about Nim instead, until I find time to continue developing the game. Easy to get running Ok, this part is not exciting yet, but I invite you to follow along with the post: for i in 0..10: echo "Hello World"[0..i] If you want to do so, get the Nim compiler. Save this code as hello.nim, compile it with nim c hello and finally run the binary with ./hello. To immediately compile and run, use nim -r c hello. To use an optimized release build instead of a debug build use nim -d:release c hello. With all of these settings you will see the following output: H He Hel Hell Hello Hello Hello W Hello Wo Hello Wor Hello Worl Hello World Run regular code at compile time To implement an efficient CRC32 procedure you need a lookup table. You could compute it at runtime or write it into your code as a magic array. Clearly we don't want any magic numbers in our code, so we'll do it at runtime (for now): import unsigned, strutils type CRC32* = uint32 const initCRC32* = CRC32(-1) proc createCRCTable(): array[256, CRC32] = for i in 0..255: var rem = CRC32(i) for j in 0..7: if (rem and 1) > 0: rem = (rem shr 1) xor CRC32(0xedb88320) else: rem = rem shr 1 result[i] = rem # Table created at runtime var crc32table = createCRCTable() proc crc32(s): CRC32 = result = initCRC32 for c in s: result = (result shr 8) xor crc32table[(result and 0xff) xor ord(c)] result = not result # String conversion proc $, automatically called by echo proc `$`(c: CRC32) ## Visualising SipHash DevFeed: [Visualising SipHash]() Original publisher: [Read original article]() Author: Marek Published: 2013-10-08T22:00:00Z Content type: tutorial Language: en Sources: [Marek Majkowski]() Topics: [Cryptography](), [hash](), [C](), [Code]() Tags: [c](), [code](), [cryptanalysis](), [hash](), [pixel](), [program](), [random](), [xor]() ### AI overview An article visualises SipHash's SipRound using differential cryptanalysis. It explains the 256-bit internal state, the operations used by SipRound, and how flipping individual input bits affects the output. ### Source excerpt Visualising SipHash Siphash is a PRF using a "SipRound" primitive as a building block. The recommended SipHash variant, SipHash-2-4, is running two SipRounds after every message block and four rounds at the end to finalise the hash. SipRound SipRound is a simple construct - it mangles 256 bits of internal state using just a few operations on 64 bit registers: - 4 bit rotations - 2 rotations by 32 bits - 4 xors - 4 additions Here's an equivalent code in C (from csiphash): Differential... ## Security doesn't respect abstraction boundaries DevFeed: [Security doesn't respect abstraction boundaries]() Original publisher: [Read original article]() Author: Nelson Elhage Published: 2010-03-13T20:20:26Z Content type: opinion Language: en Sources: [Nelson Elhage]() Topics: [Security](), [Encryption](), [Cryptography]() Tags: [abstraction](), [encryption](), [security](), [xor]() ### AI overview The article argues that computer security problems often cross or violate abstraction boundaries. It introduces one-time-pad encryption as an example and begins describing how weaknesses outside the encryption abstraction can undermine an otherwise secure system. ### Source excerpt The fundamental tool of any engineering discipline is the notion of abstraction. If we can build a set of useful, easily-described behaviors out of a complex system, we can build other systems on top of those pieces, without having to understand to worry about the full complexity of the underlying system. Without this notion of abstracting away complexity, we'd be stuck writing our webapps in assembly code - if not toggling them in to our frontpanels after painstakingly translating them into hex by hand.