# Chip design

Chip design is the engineering process of defining a semiconductor's architecture and physical layout, including circuit design, packaging, and verification.

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## Can you design a chip? Announcing the protocol emulator ASIC competition

DevFeed: [Can you design a chip? Announcing the protocol emulator ASIC competition](<https://devfeed.tech/articles/can-you-design-a-chip-announcing-the-protocol-emulator-asic-competition-20207.md>)

Original publisher: [Read original article](<https://blog.janestreet.com/protocol-emulator-asic-competition/>)

Author: Benjamin Devlin

Published: 2026-09-10T00:00:00Z

Content type: release

Language: en

Sources: [Jane Street](<https://devfeed.tech/sources/jane-street.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Protocol (disambiguation)](<https://devfeed.tech/topics/protocol.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [Open Source](<https://devfeed.tech/topics/open-source.md>), [Emulator](<https://devfeed.tech/topics/emulator.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [Reverse Engineering](<https://devfeed.tech/topics/reverse-engineering.md>), [fpga](<https://devfeed.tech/topics/fpga.md>), [Formal methods](<https://devfeed.tech/topics/formal-methods.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>)

Tags: [chip-design](<https://devfeed.tech/tags/chip-design.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [emulator](<https://devfeed.tech/tags/emulator.md>), [ethernet](<https://devfeed.tech/tags/ethernet.md>), [firmware](<https://devfeed.tech/tags/firmware.md>), [formal-methods](<https://devfeed.tech/tags/formal-methods.md>), [fpga](<https://devfeed.tech/tags/fpga.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [i2c](<https://devfeed.tech/tags/i2c.md>), [jtag](<https://devfeed.tech/tags/jtag.md>), [open-source](<https://devfeed.tech/tags/open-source.md>), [peripheral](<https://devfeed.tech/tags/peripheral.md>), [protocol](<https://devfeed.tech/tags/protocol.md>), [reverse-engineering](<https://devfeed.tech/tags/reverse-engineering.md>)

### AI overview

Jane Street announces a competition to design an open-source, general-purpose protocol emulator ASIC. The proposed chip would use a small programmable CPU to read and write pins, count cycles, and implement protocols in firmware, with fabrication planned through IHP and Tiny Tapeout.

### Source excerpt

Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here's our next challenge! This time, you're designing the chip, and we'll pay to fabricate our favorite designs! We're particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies!

## Qualcomm and Amazon Sign Multi-Generation Deal for Custom AI Inference Silicon and 1.6T Optical Interconnects

DevFeed: [Qualcomm and Amazon Sign Multi-Generation Deal for Custom AI Inference Silicon and 1.6T Optical Interconnects](<https://devfeed.tech/articles/qualcomm-and-amazon-sign-multi-generation-deal-for-custom-ai-inference-silicon-and-1-6t-optical-interconnects-12375.md>)

Original publisher: [Read original article](<https://www.storagereview.com/news/qualcomm-and-amazon-sign-multi-generation-deal-for-custom-ai-inference-silicon-and-1-6t-optical-interconnects>)

Author: Harold Fritts

Published: 2026-09-08T17:17:46Z

Content type: news

Language: en

Sources: [StorageReview.com](<https://devfeed.tech/sources/storagereview-com.md>)

Topics: [Inference](<https://devfeed.tech/topics/inference.md>), [Inference Performance](<https://devfeed.tech/topics/inference-performance.md>), [AI Infrastructure](<https://devfeed.tech/topics/ai-infrastructure.md>), [Amazon Web Services](<https://devfeed.tech/topics/aws.md>), [data centers](<https://devfeed.tech/topics/data-centers.md>), [Chip design](<https://devfeed.tech/topics/chip-design.md>), [networking](<https://devfeed.tech/topics/networking.md>), [Amazon Bedrock](<https://devfeed.tech/topics/amazon-bedrock.md>), [amazon](<https://devfeed.tech/topics/amazon.md>)

Tags: [ai](<https://devfeed.tech/tags/ai.md>), [ai-data-centers](<https://devfeed.tech/tags/ai-data-centers.md>), [ai-inference](<https://devfeed.tech/tags/ai-inference.md>), [ai-infrastructure](<https://devfeed.tech/tags/ai-infrastructure.md>), [amazon-bedrock](<https://devfeed.tech/tags/amazon-bedrock.md>), [aws](<https://devfeed.tech/tags/aws.md>), [chip-design](<https://devfeed.tech/tags/chip-design.md>), [cost](<https://devfeed.tech/tags/cost.md>), [data-centers](<https://devfeed.tech/tags/data-centers.md>), [dsp](<https://devfeed.tech/tags/dsp.md>), [efficiency](<https://devfeed.tech/tags/efficiency.md>), [enterprise](<https://devfeed.tech/tags/enterprise.md>), [networking](<https://devfeed.tech/tags/networking.md>), [partnership](<https://devfeed.tech/tags/partnership.md>), [qualcomm](<https://devfeed.tech/tags/qualcomm.md>)

### AI overview

Qualcomm Technologies and Amazon are collaborating across multiple generations to develop custom silicon for AWS AI data centers, primarily targeting AI inference. The agreement also covers 1.6T optical connectivity for data center networks and Qualcomm's use of AWS infrastructure, including Amazon Bedrock, for electronic design automation workloads.

### Source excerpt

Qualcomm Technologies and Amazon have entered into a multi-generation collaboration to deliver customized silicon at scale for AWS's AI data centers, with AI inference as the primary target. The agreement pairs Qualcomm's power-efficient processing, silicon design, and system-level integration with Amazon's AI infrastructure, and is aimed at the compute, memory bandwidth, networking, and energy constraints The post Qualcomm and Amazon Sign Multi-Generation Deal for Custom AI Inference Silicon and 1.6T Optical Interconnects appeared first on StorageReview.com.

## Google joins the OpenROAD Initiative as principal member to accelerate open source silicon innovation

DevFeed: [Google joins the OpenROAD Initiative as principal member to accelerate open source silicon innovation](<https://devfeed.tech/articles/google-joins-the-openroad-initiative-as-principal-member-to-accelerate-open-source-silicon-innovation-41367.md>)

Original publisher: [Read original article](<http://opensource.googleblog.com/2026/08/%20google-joins-the-openroad-initiative-as-principal-member-to-accelerate-open-source-silicon-innovation.html>)

Author: Google Open Source (noreply@blogger.com)

Published: 2026-08-11T18:30:00Z

Content type: release

Language: en

Sources: [Google Open Source Blog](<https://devfeed.tech/sources/google-open-source-blog.md>)

Topics: [Google](<https://devfeed.tech/topics/google.md>), [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Open Source](<https://devfeed.tech/topics/open-source.md>), [toolchains](<https://devfeed.tech/topics/toolchains.md>), [Continuous integration](<https://devfeed.tech/topics/continuous-integration.md>)

Tags: [chip-design](<https://devfeed.tech/tags/chip-design.md>), [ci-cd](<https://devfeed.tech/tags/ci-cd.md>), [eda](<https://devfeed.tech/tags/eda.md>), [google](<https://devfeed.tech/tags/google.md>), [open-source](<https://devfeed.tech/tags/open-source.md>), [openroad](<https://devfeed.tech/tags/openroad.md>), [semiconductors](<https://devfeed.tech/tags/semiconductors.md>), [toolchains](<https://devfeed.tech/tags/toolchains.md>), [user-experience](<https://devfeed.tech/tags/user-experience.md>)

### AI overview

Google has joined the OpenROAD Initiative as a principal member and appointed Aaron Cunningham to its Governing Board. The partnership supports OpenROAD's open-source electronic design automation ecosystem through governance, ecosystem growth, workforce development, and technical improvements.

### Source excerpt

by Ethan Mahintorabi & Aaron Cunningham, Hardware Toolchains Team Google is committed to advancing open source silicon innovation. We are excited to share that we have formally joined the OpenROAD Initiative (ORI), Inc. as a principal member. ORI is a nonprofit public benefit corporation dedicated to the open source electronic design automation (EDA) ecosystem. As part of this commitment, Aaron Cunningham has been appointed to the ORI Governing Board to represent Google and help drive the foundation's strategic direction, financial sustainability, and technical stewardship. Driving long-term open source sustainability The OpenROAD Initiative's mission is to advance and sustain the open source EDA ecosystem by fostering collaborative innovation across research, education, and industry--transforming ideas into silicon. Google's membership aligns directly with ORI's multi-year sustainability goals, supported by the US National Science Foundation's (NSF) Pathways to Enable Open-Source Ecosystems (POSE) program. With Google's participation and membership commitment, ORI will continue to strengthen, grow, and sustain its open source ecosystem through key vectors: Neutral Stewardship: Fostering transparent governance where no single company has outsized control over the code, ensuring the project remains inspectable, accessible, and community-driven. Ecosystem Growth: Supporting open and reproducible silicon research, developing robust design flows, and hosting global design contests. Workforce Development: Supporting global silicon skilling initiatives by expanding open source chip design curricula and collaborating with academic institutions and industrial training networks. Technical Strengthening: Enhancing continuous integration and deployment (CI/CD) pipelines, expanding PDK enablement, and improving user experience. Leadership perspectives "The OpenROAD Initiative is built on the vision of making chip design open and accessible to all--building a collaborative ecosyst

## Talking with Synopsys about the Physics of Chip Design at DAC 2026

DevFeed: [Talking with Synopsys about the Physics of Chip Design at DAC 2026](<https://devfeed.tech/articles/talking-with-synopsys-about-the-physics-of-chip-design-at-dac-2026-14005.md>)

Original publisher: [Read original article](<https://chipsandcheese.com/p/talking-with-synopsys-about-the-physics>)

Author: George Cozma

Published: 2026-08-11T16:52:16Z

Content type: article

Language: en

Sources: [Chips and Cheese](<https://devfeed.tech/sources/chips-and-cheese.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [3D](<https://devfeed.tech/topics/3d.md>), [Simulation and Design](<https://devfeed.tech/topics/simulation-and-design.md>)

Tags: [3d](<https://devfeed.tech/tags/3d.md>), [audio](<https://devfeed.tech/tags/audio.md>), [automotive](<https://devfeed.tech/tags/automotive.md>), [battery](<https://devfeed.tech/tags/battery.md>), [chip-design](<https://devfeed.tech/tags/chip-design.md>), [communications](<https://devfeed.tech/tags/communications.md>), [design](<https://devfeed.tech/tags/design.md>), [desktop](<https://devfeed.tech/tags/desktop.md>), [heat](<https://devfeed.tech/tags/heat.md>), [interview](<https://devfeed.tech/tags/interview.md>), [low-power](<https://devfeed.tech/tags/low-power.md>), [physics](<https://devfeed.tech/tags/physics.md>), [techniques](<https://devfeed.tech/tags/techniques.md>)

### AI overview

An edited audio interview with Synopsys executive Ravi Subramanian examines the physics involved in chip design and electronic design automation tools. The discussion covers larger chips, 2.5D and 3D multi-die integration, thermal management, low-power mobile systems, and automotive operating environments.

### Source excerpt

Hello you fine Internet folks,