# RISC-V RISC-V is an open standard instruction set architecture (ISA) with related specifications, enabling developers to build, port, and optimize software applications, extensions, and hardware. This is one page of public article previews, not the complete archive. Follow Next page to continue. Summaries are not the original full articles. ## Axelera Europa Ships: 629 TOPS at 45W Per AIPU, in Validated Dell XE5 and Supermicro Servers DevFeed: [Axelera Europa Ships: 629 TOPS at 45W Per AIPU, in Validated Dell XE5 and Supermicro Servers]() Original publisher: [Read original article]() Author: Harold Fritts Published: 2026-09-15T13:00:00Z Content type: news Language: en Sources: [StorageReview.com]() Topics: [Artificial Intelligence](), [Inference](), [Computer vision](), [servers](), [dell](), [RISC-V]() Tags: [ai](), [computer-vision](), [dell](), [enterprise](), [inference](), [risc-v](), [servers]() ### AI overview Axelera AI is shipping Europa, a second-generation AI Processing Unit, in bare-chip and PCIe card configurations. The company says the 45W device delivers 629 TOPS and supports on-premises inference workloads including generative AI, vision-language models, and computer vision. The Edge 232p card is shipping in validated Dell XE5 and Supermicro 111AD systems. ### Source excerpt Axelera AI is shipping Europa, the second-generation AI Processing Unit (AIPU) it has been previewing since last year, and it's launching with validated servers from Dell and Supermicro attached. The Eindhoven company's pitch is inference on infrastructure the customer controls: agentic systems, vision-language models, generative AI, and computer vision running in a standard rackmount server The post Axelera Europa Ships: 629 TOPS at 45W Per AIPU, in Validated Dell XE5 and Supermicro Servers appeared first on StorageReview.com. ## Morse Micro Wi-Fi HaLow USB adapters add 802.11ah connectivity to PCs and routers DevFeed: [Morse Micro Wi-Fi HaLow USB adapters add 802.11ah connectivity to PCs and routers]() Original publisher: [Read original article]() Author: Debashis Das Published: 2026-09-14T09:00:51Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [USB](), [Network](), [Hardware](), [RISC-V](), [Linux](), [macOS](), [Windows](), [Encryption]() Tags: [802-11ah](), [connectivity](), [documentation](), [encryption](), [firmware](), [github](), [guides](), [halow](), [hardware](), [iot](), [linux](), [lpwan](), [macos](), [network](), [networks](), [risc-v](), [security](), [usb](), [wi-fi](), [wifi](), [windows](), [wireless]() ### AI overview Morse Micro has released USB-A and USB-C Wi-Fi HaLow adapters based on its MM8108 reference design. The adapters connect PCs and routers to IEEE 802.11ah networks and support Windows, Linux, and macOS. ### Source excerpt Last year, we saw Morse Micro introduce the MM8108 Wi-Fi HaLow (802.11ah) SoC with up to 43.33 Mbps throughput, along with an MM8108-RD09 USB dongle reference design, for which we had virtually no details at the time. Morse Micro has now released USB-A and USB-C Wi-Fi HaLow adapters based on that reference design. The adapters let PCs and routers connect to 802.11ah networks through USB without a dedicated expansion card and feature an external SMA antenna delivering up to 26 dBm transmit power. Wi-Fi HaLow USB network adapter specifications: SoC - Morse Micro MM8108 32-bit RISC-V Host Applications Processor (HAP) Standard - IEEE802.11ah Wi-Fi HaLow Frequency band - 850-950 MHz (Worldwide sub-1 GHz license-exempt range) Operating Modes - Access Point (AP) and Station (STA). Channel Width - 1/2/4/8 MHz Modulation - BPSK, QPSK, 16QAM, 64QAM, 256QAM. Data rate - Up to 43.3 Mbps using 256-QAM modulation at an 8 MHz bandwidth [...] The post Morse Micro Wi-Fi HaLow USB adapters add 802.11ah connectivity to PCs and routers appeared first on CNX Software - Embedded Systems News. ## JetKVM Mini - A low-cost, ESP32-P4X-based KVM with Ethernet or WiFi connectivity DevFeed: [JetKVM Mini - A low-cost, ESP32-P4X-based KVM with Ethernet or WiFi connectivity]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-14T02:03:40Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Jetkvm](), [ESP32](), [Embedded Software Dev](), [Microcontroller](), [RISC-V](), [Web](), [WebRTC](), [networking](), [USB]() Tags: [4k](), [embedded-systems](), [esp-idf](), [esp32](), [esp32-p4](), [espressif](), [ethernet](), [firmware](), [freertos](), [github](), [hardware](), [hdmi](), [jetkvm](), [kvm](), [linux](), [macos](), [open-source](), [risc-v](), [soc](), [usb](), [video](), [webrtc](), [wifi](), [wifi-6]() ### AI overview JetKVM Mini is a smaller, lower-cost KVM over IP device based on the ESP32-P4X instead of Linux running on a Rockchip SoC. It provides Ethernet or WiFi connectivity, 1080p video capture, H.264 streaming over WebRTC, USB device emulation, and an information display. Its firmware uses FreeRTOS and ESP-IDF, while JetKVM OS Services add features such as 4K screen capture, shared clipboard, a guest terminal, and file transfer on compatible hosts. ### Source excerpt JetKVM Mini is a smaller, lower-cost version of the popular JetKVM KVM over IP solution. The new model features a small information display, offers Ethernet or WiFi connectivity, and supports 1080p video capture. The main under-the-hood change is that they ditched Linux on a Rockchip RV1106G3 SoC and now rely on an ESP32-P4X (ESP32-P4 version 3.x and greater) to handle video capture, H.264 encoding, USB, and other features. The largest cost saving is removing the RAM and eMMC flash required by Linux. JetKVM Mini specifications: SoC - Espressif Systems ESP32-P4X CPU Dual-core 32-bit RISC-V HP (High-performance) CPU @ up to 400 MHz with AI instruction extension and single-precision FPU Single-RISC-V LP (Low-power) MCU core @ up to 40 MHz Memory 768 KB HP L2MEM (for dual-core CPU), 32 KB LP SRAM, 8 KB TCM (for LP MCU core) 32 MB PSRAM Storage - 128 KB HP ROM, 16 KB LP ROM [...] The post JetKVM Mini - A low-cost, ESP32-P4X-based KVM with Ethernet or WiFi connectivity appeared first on CNX Software - Embedded Systems News. ## Infineon RISC-V for Automotive at Hot Chips 2026 DevFeed: [Infineon RISC-V for Automotive at Hot Chips 2026]() Original publisher: [Read original article]() Author: Vic A Published: 2026-09-13T21:58:44Z Content type: article Language: en Sources: [ServeTheHome]() Topics: [RISC-V](), [Microcontroller](), [real-time](), [Low Latency](), [Architecture & Design](), [Security](), [IO](), [Inference Performance]() Tags: [2026](), [architecture](), [automotive](), [compute](), [cost](), [efficiency](), [infineon](), [latency](), [low-latency](), [microcontrollers](), [mobile](), [performance](), [posix](), [processors](), [real-time](), [risc-v](), [security]() ### AI overview Infineon presents RISC-V automotive processors for next-generation vehicle architectures. The article covers real-time control, low latency, power efficiency, security, zone controllers, central car computers, and heterogeneous workloads including DSP, AI inference, audio, and POSIX-based services. ### Source excerpt At Hot Chips 2026, Infineon presented a case for using RISC-V in various automotive processors in next-generation cars The post Infineon RISC-V for Automotive at Hot Chips 2026 appeared first on ServeTheHome. ## Caught Sleeping at Work(queue) -- Zephyr Podcast #050 DevFeed: [Caught Sleeping at Work(queue) -- Zephyr Podcast #050]() Original publisher: [Read original article]() Author: Benjamin Cabé Published: 2026-09-11T12:46:06Z Content type: news Language: en Sources: [Zephyr Project]() Topics: [WebAssembly](), [qemu](), [ESP32](), [ctf](), [Espressif](), [Arduino](), [RISC-V](), [cortex m4](), [Ethernet](), [Modbus](), [USB](), [Linux]() Tags: [blog](), [ctf](), [esp32](), [espressif](), [ethernet](), [linux](), [modbus](), [perfetto](), [podcast](), [qemu](), [risc-v](), [usb](), [webassembly](), [zephyr]() ### AI overview Episode 50 of the Zephyr podcast covers the Zephyr Developer Summit schedule, Analog Devices' acquisition of Alif Semiconductor, new sensor and board support, SMP coredump improvements, CTF trace conversion to Perfetto, WebAssembly Micro Runtime documentation, and other Zephyr developments. ### Source excerpt ADI buys Alif, WebAssembly in Zephyr, CTF traces reach Perfetto, and why you should never sleep in the system workqueue. ## ESP32-C5 Pico board follows Raspberry Pi Pico form factor, ships with on-board or external antenna DevFeed: [ESP32-C5 Pico board follows Raspberry Pi Pico form factor, ships with on-board or external antenna]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-09T07:00:50Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [ESP32-C5](), [Raspberry Pi](), [Espressif](), [cpu](), [RISC-V](), [SOC](), [Bluetooth](), [wifi 6](), [zigbee](), [Matter](), [Embedded Systems](), [ESP-IDF]() Tags: [802-15-4](), [arduino](), [battery](), [ble](), [bluetooth](), [bluetooth-le](), [boot](), [c-c-plus-plus](), [development-board](), [embedded-systems](), [esp-idf](), [esp32](), [esp32-c5](), [espressif](), [gpio](), [hardware](), [iot](), [matter](), [news](), [port](), [raspberry-pi](), [risc-v](), [thread](), [usb](), [waveshare](), [wifi-6](), [zigbee]() ### AI overview The Waveshare ESP32-C5 Pico is a development board in the Raspberry Pi Pico form factor. It uses an ESP32-C5-MINI-1 series module with a RISC-V processor, dual-band WiFi 6, Bluetooth LE, and 802.15.4 support for Zigbee, Thread, and Matter. The board includes GPIO headers, USB-C, buttons, LEDs, and Li-Ion battery support, with variants offering PCB or external antennas. ### Source excerpt Waveshare ESP32-C5 Pico board brings the ESP32-C5 dual-band WiFi 6, Bluetooth LE, and 802.15.4 (Zigbee/Thread) SoC to the Raspberry Pi Pico form factor. The board features an ESP32-C5-MINI-1 Series module with PCB or external antenna, two 20-pin GPIO headers, a USB-C port for power and programming, Reset and Boot buttons, and a few LEDs. It also supports Li-Ion battery charging and discharging. Waveshare ESP32-C5 Pico specifications: Wireless module - ESP32-C5-MINI-1 or ESP32-C5-MINI-1U Wireless MCU - Espressif Systems ESP32-C5HF4 CPU Single-core 32-bit RISC-V processor @ up to 240 MHz Low-power RISC-V core @ 48 MHz acting as the main processor for power-sensitive applications Memory - 384 KB SRAM on-chip Storage - 320 KB ROM, 4MB SPI flash Wireless Dual-band (2.4/5 GHz) 802.11ax WiFi 6, 802.11b/g/n WiFi 4 backward compatibility WiFi modes: Station mode, SoftAP mode, SoftAP + Station mode, and promiscuous mode Bluetooth 5.0 Low Energy (LE) with Mesh support, up [...] The post ESP32-C5 Pico board follows Raspberry Pi Pico form factor, ships with on-board or external antenna appeared first on CNX Software - Embedded Systems News. ## YuzukiNeko - A Linux-capable Allwinner F101 RISC-V SBC with Raspberry Pi Pico form factor DevFeed: [YuzukiNeko - A Linux-capable Allwinner F101 RISC-V SBC with Raspberry Pi Pico form factor]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-07T17:01:57Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Raspberry Pi](), [Linux](), [RISC-V](), [Hardware](), [SOC](), [Embedded Systems](), [Open Source](), [Kernel](), [Software]() Tags: [allwinner](), [allwinner-d-series](), [buildroot](), [cpu](), [embedded-systems](), [gpio](), [hardware](), [linux](), [linux-7-x](), [mipi](), [open-source](), [psram](), [raspberry-pi](), [risc-v](), [single-board-computer](), [specifications](), [spi](), [storage](), [usb](), [zephyr](), [zephyr-os]() ### AI overview YuzukiHD has introduced YuzukiNeko, a Raspberry Pi Pico-sized open-source single-board computer built around the Allwinner F101 RISC-V SoC. It includes a 1.008 GHz C907 core, 8MB or 16MB PSRAM, SPI NOR flash, microSD storage, USB-C, and GPIO expansion, with support for Linux, Buildroot, and Zephyr RTOS. ### Source excerpt YuzukiHD has made another open-source hardware Linux SBC. YuzukiNeko is a Raspberry Pi Pico-sized single board computer powered by a new Allwinner F101 RISC-V SoC. The Allwinner F101 processor features a single 1.008 GHz C907 RISC-V core, 8MB or 16 MB PSRAM, and support for various display interfaces such as MIPI DSI, 24-bit RGB, and LVDS. The YuzukiNeko board itself features the F101 SoC, an SPI NOR flash, a microSD card for storage, a USB-C port, and two 20-pin GPIO headers. YuzukiNeko specifications: SoC - Allwinner F101 CPU - T-head C907 RISC-V core up to 1.008 GHz Memory - 8MB or 16MB PSRAM @ 252 MHz Package - QFN-68 Storage 128 Mbit NOR flash (PY25Q128HA-SUH-IT) MicroSD card slot USB - USB Type-C port for data, power, and programming Expansion 2x 20-pin expansion headers with GPIOs, ADC, 5V, 3.3V, and GND 5x pads with HP out (analog speaker output) and four [...] The post YuzukiNeko - A Linux-capable Allwinner F101 RISC-V SBC with Raspberry Pi Pico form factor appeared first on CNX Software - Embedded Systems News. ## Amlogic A311Y3 Cortex-A78/A55 Edge AI system-on-module delivers up to 8 TOPS DevFeed: [Amlogic A311Y3 Cortex-A78/A55 Edge AI system-on-module delivers up to 8 TOPS]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-03T13:46:18Z Content type: article Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Embedded Systems](), [Artificial Intelligence](), [cpu](), [SOC](), [GPU](), [RISC-V](), [SDK](), [Android](), [Linux]() Tags: [2025](), [4g-lte](), [amlogic](), [android](), [arm](), [boardcon](), [camera](), [compiler](), [cortex-a55](), [cortex-a78](), [cpu](), [development-board](), [development-tools](), [display](), [edge-ai](), [edge-computing](), [embedded](), [embedded-systems](), [hardware](), [linux](), [npu](), [opencl](), [risc-v](), [rs485](), [som](), [specifications](), [vulkan]() ### AI overview The article examines Boardcon's CM311Y3 system-on-module, which uses the Amlogic A311Y3 octa-core SoC with Cortex-A78 and Cortex-A55 CPUs, an 8 TOPS NPU, LPDDR5 memory, eMMC storage, and interfaces for embedded applications. It also describes the module's development board, software support, and key specifications. ### Source excerpt Boardcon CM311Y3 system-on-module (SoM) is powered by an Amlogic A311Y3 octa-core Cortex-A78/A55 SoC with an 8 TOPS NPU and targets 4K video surveillance systems, AI edge computing devices, interactive terminals, enterprise thin clients, and autonomous robots. The module comes with up to 16GB LPDDR5 and up to 256 GB eMMC flash, exposes 210 pins through castellated edges, and a development board is also provided for evaluation and early software development. We don't often see new SoMs or SBCs based on Amlogic SoCs these days, so let's have a closer look. Boardcon CM311Y3 System-on-Module CM311Y3 specifications: SoC - Amlogic A311Y3 CPU 2x ARM Cortex-A78 cores @ 2.4GHx 6x ARM Cortex-A55 cores @ 2.0GHz RISC-V core for system control processing RISC-V core for Always-on power management and Sensor Hub GPU - Arm Mali-G625 MC1 with support for OpenGL ES 3.2, Vulkan 1.4, and OpenCL 3.0 VPU Video Decoder - H.264 up to [...] The post Amlogic A311Y3 Cortex-A78/A55 Edge AI system-on-module delivers up to 8 TOPS appeared first on CNX Software - Embedded Systems News. ## Xen on RISC-V just ran on real hardware! DevFeed: [Xen on RISC-V just ran on real hardware!]() Original publisher: [Read original article]() Author: Baptiste Le Duc Published: 2026-09-03T08:00:27Z Content type: article Language: en Sources: [XCP-ng Blog]() Topics: [RISC-V](), [virtualization](), [systems](), [ci](), [cpu](), [Emulator]() Tags: [ci](), [cpu](), [qemu](), [risc-v](), [systems](), [virtualization]() ### AI overview Xen now boots a guest domain on physical RISC-V hardware using a HiFive Premier P550. Supporting changes accommodate the board's pre-ratification hypervisor extension and add reproducible hardware-based CI that boots Xen and a Linux guest. ### Source excerpt Xen now boots a guest domain on physical RISC-V hardware, not just in QEMU. The board we used ships a CPU designed before the hypervisor extension was ratified, which turned out to be the whole challenge. ## Qualcomm introduces Dragonwing Q-2390 and IQ-2390 for consumer and industrial AIoT applications DevFeed: [Qualcomm introduces Dragonwing Q-2390 and IQ-2390 for consumer and industrial AIoT applications]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-01T14:24:27Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Embedded Systems](), [cpu](), [Arm](), [RISC-V](), [GPU]() Tags: [4g-lte](), [android](), [artificial-intelligence-ai](), [camera](), [cortex-a55](), [cortex-a78](), [dsp](), [embedded](), [embedded-systems](), [hardware](), [hexagon](), [industrial](), [iot](), [linux](), [npu](), [processor](), [products](), [qualcomm](), [qualcomm-dragonwing](), [risc-v](), [ubuntu](), [wifi-5](), [yocto](), [zephyr](), [zephyr-os]() ### AI overview Qualcomm announced the Dragonwing Q-2390 and IQ-2390 quad-core Cortex-A78/A55 processors for consumer, commercial, and industrial AIoT applications. The Q-2390 targets devices such as retail and smart home products, while the IQ-2390 targets industrial automation, machine vision, building management, and energy systems. The processors include optional RISC-V real-time cores, Adreno graphics, Hexagon processing, camera and display interfaces, networking, and support for Android, Yocto Linux, Ubuntu, and Zephyr RTOS. ### Source excerpt Qualcomm has announced the Qualcomm Dragonwing Q-2390 and IQ-2390 quad-core Cortex-A78/A55 processors for AIoT consumer, commercial and industrial applications. The Dragonwing Q-2390 processor is designed for commercial and consumer devices, notably for applications such as retail and smart home products, as well as smart displays and enterprise edge devices, while the Dragonwing IQ-2390 processor is the SKU from the Dragonwing IQ2 Series designed for industrial automation, machine vision, building management and energy systems. Qualcomm IQ-2390 and Q-2390 specifications: CPU 1x Arm Cortex-A78 core up to 1.5 or 1.9 GHz depending on SKU 3x Arm Cortex-A55 cores up to 1.5 or 1.9 GHz depending on SKU Optional SiFive E61 RISC-V real-time core up to 600MHz with 768kB memory Cache - 512 KB L3 cache GPU - Qualcomm Adreno 704 up to 1.1 GHz Audio DSP - Qualcomm Hexagon V66 up to 1.1 GHz NPU - Qualcomm Hexagon up to 1.1 TOPS DPU [...] The post Qualcomm introduces Dragonwing Q-2390 and IQ-2390 for consumer and industrial AIoT applications appeared first on CNX Software - Embedded Systems News. ## ArmSoM Sige6 Allwinner A733 SBC features up to 128GB soldered-on eMMC flash, 16GB LPDDR5 DevFeed: [ArmSoM Sige6 Allwinner A733 SBC features up to 128GB soldered-on eMMC flash, 16GB LPDDR5]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-09-01T06:41:00Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Embedded Systems](), [SOC](), [cpu](), [GPU](), [RISC-V](), [real-time](), [Artificial Intelligence](), [wifi 6](), [Linux](), [Android]() Tags: [allwinner](), [allwinner-a-series](), [android](), [android-13](), [armbian](), [banana-pi](), [bluetooth](), [core](), [cortex-a55](), [cpu](), [debian](), [embedded-systems](), [gigabit-ethernet](), [gpu](), [hardware](), [hdmi](), [linux](), [npu](), [real-time](), [risc-v](), [single-board-computer](), [usb](), [wifi-6]() ### AI overview The ArmSoM Sige6 is a credit-card-sized single-board computer based on the Allwinner A733-HN3 SoC. It offers up to 16GB of LPDDR5 memory and 128GB of soldered eMMC storage, along with PCIe, Gigabit Ethernet, Wi-Fi 6, Bluetooth 5.4, display and camera interfaces, USB ports, and a 40-pin expansion header. ### Source excerpt ArmSoM Sige6 is yet another SBC powered by the Allwinner A733 octa-core SoC, offered in a credit card form factor with up to 128GB soldered-on eMMC flash and up to 16GB LPDDR5. The single board computer features a microSD card slot and an M.2 M-key PCIe 3.0 x2 slot for storage, Gigabit Ethernet (with optional PoE), WiFi 6, and Bluetooth 5.4 connectivity, HDMI 2.0 and MIPI DSI display interfaces, a MIPI CSI camera interface, USB 3.0/2.0 ports, a 3.5mm audio jack, a 40-pin GPIO header, and more. ArmSom Sige6 specifications: SoC - Allwinner A733-HN3 CPU Dual-core Arm Cortex-A76 @ up to 2.00 GHz Hexa-core Arm Cortex-A55 @ up to 1.80 GHz Single-core RISC-V E902 real-time core GPU - Imagination Technologies BXM-4-64 MC1 GPU with support for OpenGL ES 3.2, Vulkan 1.3, and OpenCL 3.0 VPU 4Kp60/8Kp24 H.265/VP9/AVS2 decoding, 4Kp30 H.264 decoding 4Kp30 H.265/H.264 encoding AI accelerator - 3 TOPS NPU Process [...] The post ArmSoM Sige6 Allwinner A733 SBC features up to 128GB soldered-on eMMC flash, 16GB LPDDR5 appeared first on CNX Software - Embedded Systems News. ## Orange Pi Zero 4 - Compact Allwinner A733 SBC offers HDMI, USB-C DP, GbE, WiFI 6, PCIe FFC connector for $26.5 and up DevFeed: [Orange Pi Zero 4 - Compact Allwinner A733 SBC offers HDMI, USB-C DP, GbE, WiFI 6, PCIe FFC connector for $26.5 and up]() Original publisher: [Read original article]() Author: Jean-Luc Aufranc (CNXSoft) Published: 2026-08-31T07:13:46Z Content type: news Language: en Sources: [CNX Software - Embedded Systems News]() Topics: [Embedded Systems](), [SOC](), [Arm](), [cpu](), [wifi 6](), [GPU](), [Bluetooth](), [RISC-V](), [hdmi](), [USB](), [Ethernet](), [OpenGL]() Tags: [allwinner](), [allwinner-a-series](), [android](), [arm](), [armbian](), [bluetooth](), [cortex-a55](), [cpu](), [debian](), [embedded-systems](), [gigabit-ethernet](), [gpu](), [h-264](), [hardware](), [hdmi](), [linux](), [npu](), [opencl](), [orange-pi](), [pcie](), [single-board-computer](), [specifications](), [ubuntu](), [usb](), [vp9](), [vulkan](), [wifi-6]() ### AI overview The Orange Pi Zero 4 is a compact single-board computer based on the Allwinner A733, with up to 8GB of memory, eMMC or UFS storage support, mini HDMI, USB-C DisplayPort, Gigabit Ethernet, Wi-Fi 6, Bluetooth 5.4, camera interfaces, GPIO, and a PCIe FFC connector. The article lists its specifications, planned operating-system images, and expected Armbian support. ### Source excerpt Orange Pi Zero 4 is an affordable yet feature-rich Allwinner A733 single board computer (SBC) with up to 8GB RAM, eMMC/UFS storage footprint, a microSD card slot, and plenty of I/Os. The board packs mini HDMI and USB-C DisplayPort, Gigabit Ethernet, WiFi 6 and Bluetooth 5.4, two MIPI CSI camera connectors, a Raspberry Pi-style PCIe FFC connector, and two GPIO headers into a compact 55x50mm form factor. Orange Pi Zero 4 specifications: SoC - Allwinner A733 CPU Dual-core Arm Cortex-A76 @ up to 2.00 GHz Hexa-core Arm Cortex-A55 @ up to 1.79 GHz Single-core RISC-V E902 real-time core up to 200 MHz GPU - Imagination Technologies BXM-4-64 MC1 GPU with support for OpenGL ES 3.2, Vulkan 1.3, OpenCL 3.0 VPU 8Kp24 H.265/VP9/AVS2 decoding 4Kp30 H.265/H.264 encoding AI accelerator - 3 TOPS NPU System Memory - 1GB, 2GB, 4GB, 6GB, or 8GB LPDDR5/LPDDR4/LPDDR4x; note: 16GB is also listed in the specs, [...] The post Orange Pi Zero 4 - Compact Allwinner A733 SBC offers HDMI, USB-C DP, GbE, WiFI 6, PCIe FFC connector for $26.5 and up appeared first on CNX Software - Embedded Systems News. ## Hot Chips 2026: XCENA and Samsung's Near-Memory Compute CXL Device DevFeed: [Hot Chips 2026: XCENA and Samsung's Near-Memory Compute CXL Device]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-30T07:25:37Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [samsung](), [ddr5](), [RISC-V](), [data](), [Cache](), [Arm](), [intel]() Tags: [2026](), [arm](), [cache](), [capacity](), [clusters](), [compute](), [core](), [ddr5](), [dram](), [intel](), [memory](), [parallel](), [pcie](), [performance](), [risc-v](), [samsung]() ### AI overview The article examines XCENA and Samsung's MX1, a CXL memory expansion device that can host up to 2 TB of DDR5 memory, connect SSDs, and provide onboard compute through 3,072 RISC-V cores. It describes the device's memory bandwidth, cache hierarchy, power use, and focus on data-parallel workloads. ### Source excerpt CXL memory expansion, with a side of compute ## SiFive's First Server Platform DevFeed: [SiFive's First Server Platform]() Original publisher: [Read original article]() Author: George Cozma Published: 2026-08-25T01:48:39Z Content type: comparison Language: en Sources: [Chips and Cheese]() Topics: [RISC-V](), [servers](), [cpu](), [ddr5](), [Ubuntu](), [intel]() Tags: [cpu](), [ddr5](), [intel](), [performance](), [risc-v](), [server](), [ubuntu]() ### AI overview The article examines SiFive's BigSky SF-2U870, a 2U RISC-V server platform with 32 P870-D cores, DDR5 memory, PCIe connectivity, GPU support, and storage. It describes the platform as easy to deploy, highlights RVA23 and Ubuntu 26.04 support, and compares its specifications with Intel's Xeon 6532P-B and AMD EPYC 8325P. ### Source excerpt Hello you fine Internet folks, ## Hot Chips 2026: CUDA Targets RISC-V DevFeed: [Hot Chips 2026: CUDA Targets RISC-V]() Original publisher: [Read original article]() Author: Chester Lam Published: 2026-08-24T16:49:25Z Content type: article Language: en Sources: [Chips and Cheese]() Topics: [CUDA](), [RISC-V](), [Nvidia](), [GPU](), [Software]() Tags: [cache](), [cuda](), [framework](), [gpu](), [nvidia](), [pcie](), [risc-v](), [software](), [uefi]() ### AI overview The article reports that Nvidia is exploring support for CUDA on RISC-V CPUs. It describes requirements including RVA23, server SoC and platform specifications, RISC-V ACPI support, vector extensions, and PCIe coherency to support reliable and efficient GPU compute. ### Source excerpt CUDA is the most important software framework in the GPU compute world, and Nvidia is looking at supporting CUDA on RISC-V. Terms and conditions may apply. ## RISC-V is now officially supported by CPython! DevFeed: [RISC-V is now officially supported by CPython!]() Original publisher: [Read original article]() Author: Stan Ulbrych Published: 2026-08-24T00:00:00Z Content type: news Language: en Sources: [Python Insider]() Topics: [RISC-V](), [Python](), [Hardware](), [ci]() Tags: [ci](), [community](), [contributed](), [contributors](), [hardware](), [platform](), [python](), [testing]() ### AI overview CPython now officially supports RISC-V as a tier 3 platform. The article describes the community contributions, real-hardware testing, and build support that enabled the milestone, as well as plans to integrate RISC-V into CPython's CI and eventually pursue tier 2 support. ### Source excerpt I'm happy to announce that RISC-V platforms are now officially supported by CPython. 🎉 🚀 ## ESP-BIST in Action: A Self-Testing HMI using ESP32-P4 DevFeed: [ESP-BIST in Action: A Self-Testing HMI using ESP32-P4]() Original publisher: [Read original article]() Author: John Lee Published: 2026-08-22T00:00:00Z Content type: tutorial Language: en Sources: [Blog on Developer Portal]() Topics: [ESP32-P4](), [Testing](), [Test coverage](), [Espressif](), [Microcontroller](), [RISC-V](), [boot]() Tags: [blog](), [display](), [esp32-p4](), [espressif](), [hmi](), [lvgl](), [modbus](), [risc-v](), [safety](), [startup](), [test-coverage](), [testing]() ### AI overview This tutorial explains how ESP-BIST provides IEC 60730 Class B self-test coverage on Espressif SoCs. It demonstrates an ESP32-P4-powered HMI using an M5Stack Tab5, Modbus communication with a simulated motor controller, and an LVGL touchscreen. The article describes post-boot and runtime tests, safe-state handling, and Host Diagnostics using the low-power RISC-V core. ### Source excerpt ESP-BIST brings IEC 60730 Class B self-test coverage to Espressif SoCs, and this article walks through what that actually means before putting it to work. Using an ESP32-P4-based M5Stack Tab5 as a Modbus HMI for a simulated motor controller, we show how a SoC that can prove its own health is a chip you can trust to draw a "safe" screen without lying about it. ## QEMU version 11.1.0 released DevFeed: [QEMU version 11.1.0 released]() Original publisher: [Read original article]() Published: 2026-08-11T23:56:00Z Content type: release Language: en Sources: [QEMU]() Topics: [qemu](), [virtualization](), [version](), [Availability](), [Arm](), [cpu](), [RISC-V](), [virtio]() Tags: [announce](), [arm](), [availability](), [bugs](), [cache](), [changelog](), [ci](), [cpu](), [documentation](), [gui](), [qemu](), [qemu-11-1](), [release](), [releases](), [risc-v](), [testing](), [version](), [virtio](), [virtualization]() ### AI overview QEMU 11.1.0 has been released with more than 3,200 commits from 285 authors. The release adds or improves emulation, virtualization, GUI, architecture, firmware, and accelerator support, including UFS features, ARM and RISC-V capabilities, nested virtualization, and new machine and board support. ### Source excerpt We'd like to announce the availability of the QEMU 11.1.0 release. This release contains 3200+ commits from 285 authors. ## Xen 4.22: Strengthening Open Source Virtualization for Cloud, Embedded, and Automotive Systems DevFeed: [Xen 4.22: Strengthening Open Source Virtualization for Cloud, Embedded, and Automotive Systems]() Original publisher: [Read original article]() Author: Cody Zuschlag Published: 2026-08-05T15:18:36Z Content type: article Language: en Sources: [Blog - Xen Project]() Topics: [virtualization](), [Open Source](), [Cloud](), [Hardware](), [Scalability](), [Arm](), [RISC-V]() Tags: [arm](), [automotive](), [cloud](), [developers](), [embedded](), [hardware](), [improvements](), [lifecycle](), [maintenance](), [open-source](), [performance](), [platform](), [release](), [releases](), [risc-v](), [safety](), [security](), [standards](), [systems](), [virtualization](), [xen-4-22]() ### AI overview Xen 4.22 is presented as the latest Xen hypervisor release, adding modern hardware support, Arm virtualization improvements, continued RISC-V progress, and Xenstore scalability updates. The Xen Project also introduces a consistent five-year security support lifecycle for Xen 4.20 and later releases. ### Source excerpt Xen 4.22 adds modern hardware support, Arm improvements, continued RISC-V progress, Xenstore scalability updates, and a five-year security support lifecycle. ## Community Update - Week 27 DevFeed: [Community Update - Week 27]() Original publisher: [Read original article]() Author: lenkaseg Published: 2026-07-03T11:00:00Z Content type: news Language: en Sources: [Fedora Community Blog]() Topics: [Fedora](), [release engineering](), [RISC-V](), [forgejo](), [scaleway]() Tags: [ai](), [centos-stream](), [community-update](), [fedora-project-community](), [forgejo](), [hardware](), [release-engineering](), [report](), [risc-v](), [scaleway]() ### AI overview A Fedora CLE Team report covering community work from 29 June to 3 July 2026. It summarizes infrastructure operations, CentOS infrastructure, release engineering, RISC-V hardware and builder efforts, migration work, process discussions, packager 2FA discussions, meetings, and an AI-related script improvement. ### Source excerpt This is a report created by CLE Team, which is a team containing community members working in various Fedora groups for example Infrastructure, Release Engineering, Quality etc. This team is also moving forward some initiatives inside Fedora project. Week: 29 June - 3 July 2026 Fedora Infrastructure This team is taking care of day to [...] The post Community Update - Week 27 appeared first on Fedora Community Blog. ## AES67 audio-over-IP on the ESP32-P4 DevFeed: [AES67 audio-over-IP on the ESP32-P4]() Original publisher: [Read original article]() Author: John Lee Published: 2026-06-24T00:00:00Z Content type: tutorial Language: en Sources: [Blog on Developer Portal]() Topics: [ESP32-P4](), [ESP-IDF](), [Ethernet](), [Latency](), [RISC-V](), [Protocol (disambiguation)](), [Toit](), [Raspberry Pi]() Tags: [aes67](), [audio](), [blog](), [esp-idf](), [esp32](), [esp32-p4](), [ethernet](), [hardware](), [ip](), [latency](), [low-latency](), [network](), [networking](), [protocol](), [ptp](), [ravenna](), [risc-v](), [rtp](), [sync]() ### AI overview This article describes implementing a working, PTP-synchronized AES67/RAVENNA audio endpoint on the ESP32-P4 as an ESP-IDF component. It covers clock synchronization, low-latency packet reception, and I2S playout, reporting best-case end-to-end latency of about 0.7 ms and noting which parts are solid or still limited. ### Source excerpt AES67/RAVENNA is the audio transport behind a lot of broadcast and live-sound infrastructure, and it normally runs on dedicated silicon or Linux boxes. This article is about getting a working, PTP-synchronized AES67 endpoint onto an ESP32-P4 -- how the clock sync, the low-latency receive path, and the I2S playout fit together, what the measured latency is, and where the edges are. ## 【eBPF 内核实现深度拆解】从验证器到 JIT，从 BTF 到调度器 DevFeed: [【eBPF 内核实现深度拆解】从验证器到 JIT，从 BTF 到调度器]() Original publisher: [Read original article]() Author: Liao Tonglang Published: 2026-06-12T00:00:00Z Content type: article Language: zh Sources: [土法炼钢 - 系统与基础设施]() Topics: [eBPF](), [Linux](), [JIT](), [Benchmark](), [clang](), [hash](), [benchmarking](), [RISC-V](), [ast-matchers]() Tags: [arm](), [array](), [benchmark](), [bpf-jit](), [bpf-maps](), [bpf-verifier](), [btf](), [clang](), [co-re](), [cpu](), [ebpf](), [fentry](), [hash](), [jit](), [kernel](), [libbpf](), [linux](), [linux-kernel](), [precision](), [risc-v](), [sched-ext](), [trampoline](), [x86](), [xdp]() ### AI overview This Chinese-language series systematically explains eBPF's Linux kernel implementation, covering the BPF instruction set and registers, verifier algorithms, JIT compilation, map data structures and concurrency, helper type checking, BTF and CO-RE relocation, libbpf loading, trampolines, and sched_ext interfaces. It is aimed at engineers who want to understand eBPF kernel source code and build production BPF programs. ### Source excerpt eBPF 内核虚拟机内部实现系统讲解：BPF 指令集与寄存器机器、验证器的抽象解释与状态裁剪、JIT 编译器后端、Map 各类型的并发与内存模型、helper 函数注册与类型检查、BTF 格式规范与 CO-RE 重定位引擎、libbpf 加载器工程、fentry/fexit 蹦床机制、sched_ext 调度器内核接口。面向想读懂 eBPF 内核源码、写生产级 BPF 程序的系统工程师。 ## Xen on RISC-V: Dom0 Boot, Hypercalls and Docker Toolchain DevFeed: [Xen on RISC-V: Dom0 Boot, Hypercalls and Docker Toolchain]() Original publisher: [Read original article]() Author: Baptiste Le Duc Published: 2026-05-22T08:30:21Z Content type: article Language: en Sources: [XCP-ng Blog]() Topics: [RISC-V](), [Docker](), [Tooling](), [Command-line interface]() Tags: [asynchronous](), [boot](), [command-line](), [communication](), [docker](), [interrupt](), [memory](), [risc-v](), [tooling]() ### AI overview This first post in a series reports progress on bringing Xen guest-domain support to RISC-V. It describes Dom0 boot work, hypercall communication through SBI ecall, event-channel notifications, and a Docker environment for building and running the stack on an x86 laptop. ### Source excerpt Latest progress on Xen for RISC-V, including Dom0 boot, hypercalls and Docker-based tooling. ## QEMU version 11.0.0 released DevFeed: [QEMU version 11.0.0 released]() Original publisher: [Read original article]() Published: 2026-04-22T16:11:00Z Content type: release Language: en Sources: [QEMU]() Topics: [qemu](), [version](), [virtualization](), [systems](), [x86](), [Arm](), [RISC-V](), [cpu](), [virtio](), [C++](), [gdb]() Tags: [arm](), [availability](), [c-plus-plus](), [changelog](), [ci](), [cpu](), [documentation](), [download](), [gdb](), [kvm](), [qemu](), [qemu-11-0](), [release](), [releases](), [risc-v](), [testing](), [updates](), [virtio](), [virtualization](), [x86]() ### AI overview QEMU 11.0.0 is released with more than 2,500 commits from 237 authors. Highlights include a new Nitro accelerator for AWS Nitro Enclaves, expanded accelerator and confidential VM support, new architecture features, and updates to device emulation, plugins, drivers, and debugging. ### Source excerpt We'd like to announce the availability of the QEMU 11.0.0 release. This release contains 2500+ commits from 237 authors. [Next page]()