# Verilog

Verilog is a hardware description language used to model, simulate, and synthesize digital electronic systems.

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## Can you design a chip? Announcing the protocol emulator ASIC competition

DevFeed: [Can you design a chip? Announcing the protocol emulator ASIC competition](<https://devfeed.tech/articles/can-you-design-a-chip-announcing-the-protocol-emulator-asic-competition-20207.md>)

Original publisher: [Read original article](<https://blog.janestreet.com/protocol-emulator-asic-competition/>)

Author: Benjamin Devlin

Published: 2026-09-10T00:00:00Z

Content type: release

Language: en

Sources: [Jane Street](<https://devfeed.tech/sources/jane-street.md>)

Topics: [Chip design](<https://devfeed.tech/topics/chip-design.md>), [Protocol (disambiguation)](<https://devfeed.tech/topics/protocol.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [Open Source](<https://devfeed.tech/topics/open-source.md>), [Emulator](<https://devfeed.tech/topics/emulator.md>), [cpu](<https://devfeed.tech/topics/cpu.md>), [Reverse Engineering](<https://devfeed.tech/topics/reverse-engineering.md>), [fpga](<https://devfeed.tech/topics/fpga.md>), [Formal methods](<https://devfeed.tech/topics/formal-methods.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>)

Tags: [chip-design](<https://devfeed.tech/tags/chip-design.md>), [cpu](<https://devfeed.tech/tags/cpu.md>), [emulator](<https://devfeed.tech/tags/emulator.md>), [ethernet](<https://devfeed.tech/tags/ethernet.md>), [firmware](<https://devfeed.tech/tags/firmware.md>), [formal-methods](<https://devfeed.tech/tags/formal-methods.md>), [fpga](<https://devfeed.tech/tags/fpga.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [i2c](<https://devfeed.tech/tags/i2c.md>), [jtag](<https://devfeed.tech/tags/jtag.md>), [open-source](<https://devfeed.tech/tags/open-source.md>), [peripheral](<https://devfeed.tech/tags/peripheral.md>), [protocol](<https://devfeed.tech/tags/protocol.md>), [reverse-engineering](<https://devfeed.tech/tags/reverse-engineering.md>)

### AI overview

Jane Street announces a competition to design an open-source, general-purpose protocol emulator ASIC. The proposed chip would use a small programmable CPU to read and write pins, count cycles, and implement protocols in firmware, with fabrication planned through IHP and Tiny Tapeout.

### Source excerpt

Last month, we asked you to reverse engineer a chip from nothing but its layout and teased a bigger challenge. Results and our favorite writeups are coming soon. In the meantime, here's our next challenge! This time, you're designing the chip, and we'll pay to fabricate our favorite designs! We're particularly interested in projects with unique functionality, as well as those that demonstrate novel approaches to design and verification methodologies!

## Reverse-engineer an ASIC from its chip layout

DevFeed: [Reverse-engineer an ASIC from its chip layout](<https://devfeed.tech/articles/can-you-reverse-engineer-an-asic-20156.md>)

Original publisher: [Read original article](<https://blog.janestreet.com/can-you-reverse-engineer-an-asic/>)

Author: Anish Singhani

Published: 2026-08-05T00:00:00Z

Content type: article

Language: en

Sources: [Jane Street](<https://devfeed.tech/sources/jane-street.md>)

Topics: [Hardware](<https://devfeed.tech/topics/hardware.md>), [Reverse Engineering](<https://devfeed.tech/topics/reverse-engineering.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>), [Routing (disambiguation)](<https://devfeed.tech/topics/routing.md>), [Code](<https://devfeed.tech/topics/code.md>)

Tags: [code](<https://devfeed.tech/tags/code.md>), [design-automation](<https://devfeed.tech/tags/design-automation.md>), [engineering](<https://devfeed.tech/tags/engineering.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [puzzle](<https://devfeed.tech/tags/puzzle.md>), [reverse-engineering](<https://devfeed.tech/tags/reverse-engineering.md>), [routing](<https://devfeed.tech/tags/routing.md>), [signal](<https://devfeed.tech/tags/signal.md>)

### AI overview

Jane Street presents a puzzle that challenges readers to reverse-engineer an ASIC from its physical chip layout, recover the underlying netlist, determine the circuit's purpose, and derive a final answer from its output.

### Source excerpt

Earlier this year we published a puzzle that handed you a complete neural network and asked you to figure out what it did. The response was great, so we've made another one! This time, we're going much deeper down the tech stack. For this puzzle we've designed a chip, but we're only giving you the layout. A crash course in how chips get made Modern chips start life as code.

## NVIDIA Nemotron 3 Ultra Leads Open Models on Accuracy and Efficiency in Agentic RTL Coding

DevFeed: [NVIDIA Nemotron 3 Ultra Leads Open Models on Accuracy and Efficiency in Agentic RTL Coding](<https://devfeed.tech/articles/nvidia-nemotron-3-ultra-leads-open-models-on-accuracy-and-efficiency-in-agentic-rtl-coding-6901.md>)

Original publisher: [Read original article](<https://developer.nvidia.com/blog/nvidia-nemotron-3-ultra-leads-open-models-on-accuracy-and-efficiency-in-agentic-rtl-coding/>)

Author: Nirmal Kumar Juluru

Published: 2026-07-27T00:45:00Z

Content type: article

Language: en

Sources: [NVIDIA Developer](<https://devfeed.tech/sources/nvidia-developer.md>), [NVIDIA Technical Blog](<https://devfeed.tech/sources/nvidia-technical-blog.md>)

Topics: [coding](<https://devfeed.tech/topics/coding.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>), [AI-assisted coding](<https://devfeed.tech/topics/ai-assisted-coding.md>), [Nvidia](<https://devfeed.tech/topics/nvidia.md>), [Artificial Intelligence](<https://devfeed.tech/topics/ai.md>), [debugging](<https://devfeed.tech/topics/debugging.md>), [Benchmark](<https://devfeed.tech/topics/benchmark.md>), [Code generation](<https://devfeed.tech/topics/code-generation.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [long-context](<https://devfeed.tech/topics/long-context.md>)

Tags: [agentic](<https://devfeed.tech/tags/agentic.md>), [agentic-ai-generative-ai](<https://devfeed.tech/tags/agentic-ai-generative-ai.md>), [ai](<https://devfeed.tech/tags/ai.md>), [ai-agent](<https://devfeed.tech/tags/ai-agent.md>), [ai-agents](<https://devfeed.tech/tags/ai-agents.md>), [automation](<https://devfeed.tech/tags/automation.md>), [benchmark](<https://devfeed.tech/tags/benchmark.md>), [chip-design](<https://devfeed.tech/tags/chip-design.md>), [code](<https://devfeed.tech/tags/code.md>), [code-generation](<https://devfeed.tech/tags/code-generation.md>), [coding](<https://devfeed.tech/tags/coding.md>), [debugging](<https://devfeed.tech/tags/debugging.md>), [developer-tools-techniques](<https://devfeed.tech/tags/developer-tools-techniques.md>), [efficiency](<https://devfeed.tech/tags/efficiency.md>), [engineering](<https://devfeed.tech/tags/engineering.md>), [featured](<https://devfeed.tech/tags/featured.md>), [hardware-semiconductor](<https://devfeed.tech/tags/hardware-semiconductor.md>), [llms](<https://devfeed.tech/tags/llms.md>), [long-context](<https://devfeed.tech/tags/long-context.md>), [models](<https://devfeed.tech/tags/models.md>), [nemotron](<https://devfeed.tech/tags/nemotron.md>), [nvidia](<https://devfeed.tech/tags/nvidia.md>), [open](<https://devfeed.tech/tags/open.md>), [reasoning](<https://devfeed.tech/tags/reasoning.md>), [top-stories](<https://devfeed.tech/tags/top-stories.md>), [validation](<https://devfeed.tech/tags/validation.md>)

### AI overview

NVIDIA's article presents ACE-RTL and Nemotron 3 Ultra as a combined approach to agentic RTL coding. The workflow generates Verilog, runs simulations and other EDA checks, analyzes failures, and iteratively refines designs while maintaining debugging context. The CVDP benchmark evaluates accuracy and efficiency on realistic RTL generation, modification, debugging, and verification tasks.

### Source excerpt

Modern chip design is increasingly limited by engineering time. Register transfer level (RTL) development and verification require specialized hardware...

## Results from the Advent of FPGA Challenge

DevFeed: [Results from the Advent of FPGA Challenge](<https://devfeed.tech/articles/results-from-the-advent-of-fpga-challenge-20148.md>)

Original publisher: [Read original article](<https://blog.janestreet.com/advent-of-fpga-challenge-2025-results/>)

Author: Anish Singhani

Published: 2026-02-11T00:00:00Z

Content type: article

Language: en

Sources: [Jane Street](<https://devfeed.tech/sources/jane-street.md>)

Topics: [fpga](<https://devfeed.tech/topics/fpga.md>), [Advent of Code](<https://devfeed.tech/topics/advent-of-code.md>), [Hardware](<https://devfeed.tech/topics/hardware.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>), [Algorithms](<https://devfeed.tech/topics/algorithms.md>)

Tags: [advent-of-code](<https://devfeed.tech/tags/advent-of-code.md>), [algorithms](<https://devfeed.tech/tags/algorithms.md>), [competition](<https://devfeed.tech/tags/competition.md>), [fpga](<https://devfeed.tech/tags/fpga.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [writeup](<https://devfeed.tech/tags/writeup.md>)

### AI overview

Jane Street reports the results of its Advent of FPGA Challenge, a hardware-design competition run alongside Advent of Code. The article describes participation statistics, the hardware description languages used, and examples of notable submissions.

### Source excerpt

At the end of last year, we decided to try something new: a challenge that would run alongside Advent of Code, where we asked the community to show us how they could design hardware to solve the same problems. We had no idea what level of participation to expect, but we received a huge number of submissions, many of which were incredibly creative!

## Growing the Hardcaml toolset

DevFeed: [Growing the Hardcaml toolset](<https://devfeed.tech/articles/growing-the-hardcaml-toolset-20172.md>)

Original publisher: [Read original article](<https://blog.janestreet.com/growing-the-hardcaml-toolset-index/>)

Author: Andrew Ray

Published: 2020-12-01T00:00:00Z

Content type: release

Language: en

Sources: [Jane Street](<https://devfeed.tech/sources/jane-street.md>)

Topics: [Library](<https://devfeed.tech/topics/library.md>), [Documentation](<https://devfeed.tech/topics/documentation.md>), [fpga](<https://devfeed.tech/topics/fpga.md>), [Markdown](<https://devfeed.tech/topics/markdown.md>), [OCaml](<https://devfeed.tech/topics/ocaml.md>), [Testing](<https://devfeed.tech/topics/testing.md>), [Simulation](<https://devfeed.tech/topics/simulation.md>), [Verilog](<https://devfeed.tech/topics/verilog.md>)

Tags: [announce](<https://devfeed.tech/tags/announce.md>), [documentation](<https://devfeed.tech/tags/documentation.md>), [fpga](<https://devfeed.tech/tags/fpga.md>), [hardware](<https://devfeed.tech/tags/hardware.md>), [libraries](<https://devfeed.tech/tags/libraries.md>), [markdown](<https://devfeed.tech/tags/markdown.md>), [ocaml](<https://devfeed.tech/tags/ocaml.md>), [simulation](<https://devfeed.tech/tags/simulation.md>), [sorting](<https://devfeed.tech/tags/sorting.md>), [testing](<https://devfeed.tech/tags/testing.md>)

### AI overview

Jane Street announces a broad set of new Hardcaml libraries, expanded documentation, and improved testing support. The release includes circuit designs, FPGA component bindings, verification tools, simulator backends, Verilog import, and additional simulation and hardware-design utilities.

### Source excerpt

I am pleased to announce that we have recently released a slew of new Hardcaml libraries!